ISSUE 4.2 : November 1998
PUMA 68F4006/A-70/90/12
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
The following table defines these register command sequences.
Bus
Write
Cycles
Req'd
Fourth Bus
Read/Write
Cycle
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Command
Sequence
Read/Reset
Addr
Data
Addr
Data
Addr
Data
F0H
Addr
Data
Addr
Data
Addr
Data
Read/Reset
3
3
4
5555H
5555H
5555H
5555H
5555H
AAH
AAH
AAH
AAH
AAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
55H
55H
55H
55H
55H
5555H
5555H
5555H
5555H
5555H
RA
RD
01H/20H
PD
XX00H/
XX01H
Autoselect
90H
A0H
80H
80H
Byte Program
Chip Erase
Sector Erase
PA
2AAAH
2AAAH
5555H
5555H
AAH
AAH
55H
55H
5555H
SA
10H
30H
6
6
NOTES:
1. Address bit A15=X=Don't care.
2. Address bit A16=X=Don't care for all address commands except for Program Address (PA)
and Sector Address (SA).
3. RA=Address of the memory location to be read.
PA=Address of memory location to be programmed. Addresses are latched on the falling edge of the WE pulse .
SA=Address of the sector to be erased. The combination of A16, A15 and A14 will uniquely select any
sector.
4. RD=Data read from location RA during read operation.
PD=Data to be programmed at location PA. Data is latched on the rising edge of WE
Read / Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for
reads until the command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for specific timing parameters.
14
MOSAIC [ MOSAIC ]
