512K x 8 SRAM
MSM8512 - 70/85/10
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.3 : January 1999
Description
The MSM8512 is a 4Mbit monolithic SRAM
organised as 512K x 8 with access times from
70ns to 100ns available. The device is available in
three 32 pin ceramic packages, one being the
space saving VIL
TM
. The device has a low power
standby version which supports data retention
mode and is directly TTL compatible.
All versions can be screened in accordance with
MIL-STD-883C.
524,288 x 8 CMOS Static RAM
Features
Fast Access Times of 70/85/100 ns
JEDEC standard package.
Average Operating Power 385 mW (max)
Standby Power
550
µW
(max) -L version
Low voltage data retention.
Completely Static Operation
Directly TTL compatible
May be processed in accordance with MIL-STD-883C
Block Diagram
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
D0
D7
WE
OE
CS
Pin Definition
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D0
A0
A1
A2
A3
A4
A5
A6
A7
32
31
30
29
28
27
4,194,304
BIT
MEMORY
ARRAY
S,V
Package
Top View
26
25
24
23
22
21
20
19
18
17
I/O
BUFFER
COLUMN I/O
COLUMN DECODE
Y ADDRESS BUFFER
Vcc
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
X ADDRESS BUFFER
ROW DECODE
13
12
11
10
9
8
7
6
5
D1
D2
GND
D3
D4
D5
D6
Package Details
Pin Count
32
32
32
Descripion
Package Type
S
V
J
0.6" Dual-in-Line (DIP)
0.1" Vertical-in-line (VIL
TM
)
Extended JLCC Package
Pin Functions
A0-A18
Address Inputs
D0-7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
Power (+5V)
V
CC
GND
Ground
A17
A10
OE
A11
A9
A8
A13
WE
D7
21
22
23
24
25
26
27
28
29
14
15
16
17
18
19
20
A8
A7
A6
A5
A4
A3
A2
A1
A0
TOP VIEW
J
4
3
2
1
32
31
30
A12
A14
A16
A18
VCC
A15
CS2
MOSAIC [ MOSAIC ]
