MSM832 - 70/85/10
ISSUE 4.4 : November 1998
32K x 8 SRAM
MSM832 - 70/85/10
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.4 : Nov 1998
Description
The MSM832 is a Static RAM organised as 32K x
8 available with access times of 70,85 or 100 ns.
The device is available in five ceramic package
options including the high denisty VIL™ package.
It features completely static operation with a low
power standby mode and is 3.0V battery back-up
compatible. It is directly TTL compatible and has
common data inputs and outputs.
The device may be screened in accordance with
MIL-STD-883.
32,768 x 8 CMOS Static RAM
Features
• Fast Access Times of 70/85/100 ns.
• JEDEC Standard footprint.
• Low Power Operation : 385 mW (max)
• Low Power Standby : 1.1 mW (max) -L version.
• Low Voltage Data Retention.
• Directly TTL compatible.
• Completely Static Operation.
Block Diagram
Pin Definitions
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6 TOP VIEW
7 PACKAGE
8
V,T,S
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
E
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
A3
A4
A5
A6
A7
A8
A12
A13
A14
X
Address
Buffer
Row
Decoder
Memory Array
512 X 512
D0
D7
I/O
Buffer
Column I/O
Column Decoder
WE
OE
Y Address Buffer
A6
A5
A4
A3
A2
A1
A0
NC
D0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
A7
A12
A14
NC
Vcc
WE
A13
CS
J,W
PACKAGE
TOP VIEW
A8
A9
A11
NC
OE
A10
CS
D7
D6
A0
A1
A2
A9
A10
A11
20
19
18
17
16
15
14
D5
D4
D3
NC
GND
D2
D1
Package Details
Pin Count
28
28
28
32
32
Description
Package Type
V
T
S
J
W
0.1" Vertical-in-Line (VIL
TM
)
0.3" Dual-in-line (SKINNY DIP)
0.6"Dual-in-Line (DIP)
J-Leaded Chip Carrier (JLCC)
Leadless Chip Carrier (LCC)
Pin Functions
A0-A14
Address inputs
D0-7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
V
CC
Power(+5V)
GND
Ground
1
MOSAIC [ MOSAIC ]
