ISSUE 4.4 : November 1998
MSM832 - 70/85/10
(5)
Write Cycle No.2 Timing Waveform
t
WC
Address
t
CW
CS
(6)
(4)
t
AW
t
WP(1)
WE
t
WR(2)
t
AS(3)
t
WHZ(3,9)
t
OW
High-Z
t
DW
t
OH
(8)
(7)
Dout
t
DH
Din
High-Z
Data Valid
Data Retention Waveform
Vcc
4.5V
DATA RETENTION MODE
4.5V
t
CDR
V
DR
CS
0V
t
R
2.2V
CS>Vcc-0.2V
AC Write Characteristics Notes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
A write occurs during the overlap (t
WP
) of a low CS and a low WE.
t
WR
is measured from the earlier of CS or WE going high to the end of write cycle.
During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs
remain in a high impedance state.
OE is continuously low. (OE=V
IL
)
Dout is in the same phase as written data of this write cycle.
Dout is the read data of next address.
If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied
to I/O pins.
t
WHZ
and t
OHZ
is defined as the time at which the outputs achieve the open circuit conditions and is not referenced
to output voltage levels. This parameter is sampled and not 100% tested.
6
MOSAIC [ MOSAIC ]
