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MFM8516J-12 参数 Datasheet PDF下载

MFM8516J-12图片预览
型号: MFM8516J-12
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 512KX8, 120ns, CQCC32, CERAMIC, JLCC-32]
分类和应用: 内存集成电路
文件页数/大小: 25 页 / 237 K
品牌: MOSAIC [ MOSAIC ]
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ISSUE 4.7 : NOVEMBER 1998  
MFM8516 - 70/90/12/15  
DEVICE OPERATION  
Read Mode  
The MFM8516 has two control functions which must be satisfied in order to obtain data at the outputs  
CS is the power control and should be used for device selection.  
OE is the output control and should be used to gate data to the output pins if the device is selected.  
Standby Mode  
Two standby modes are available : CMOS standby : CS held at Vcc +/- 0.5V  
TTL standby :  
CS held at VIH  
In the standby mode the outputs are in a high impedance state independent of the OE input. If the device is  
deselected during erasure or programming the device will draw active current until the operation is completed.  
Output Disable  
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins  
to be in a high impedance state.  
Autoselect  
This mode is intended for use by programming equipment. This mode is functional over the full military  
temperature range. The autoselect codes as follows :  
Type  
A18  
A17  
A16  
A6  
A1  
A0  
Code  
(HEX)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Sector  
Protection  
Sector Address  
VIL  
VIH  
VIL  
01H*  
0
0
0
0
0
0
0
1
* Outputs 01H at protected sector address  
To activate this mode the programming equipment must force VID on address A9 . All addresses are don't  
care apart from A0, A1 & A6.  
Write  
Device erasure and programming are accomplished via the command register. The contents of the register  
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device.  
The register is a latch used to store the commands along with the address and data information required to  
execute the command. The command register is written by bringing WE to VIL while CS is at VIL and  
OE is at VIH. Addresses are latched on the falling edge of WE or CS, whichever happens later; while data is  
latched on the rising edge of WE or CS, whichever happens first.  
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