MS6713
MOSA
3 Stereo Inputs / 4 Channels Output Audio Processor
I2C BUS DESCRIPTION
Start and Stop Conditions
A start condition is activated when the SCL is set to HIGH and SDA shifts from HIGH to LOW state. The stop
condition is activated when SCL is set to HIGH and SDA shifts from LOW to HIGH state. Please refer to the timing
diagram below.
SCL
SDA
Start
Stop
SCL : Serial Clock Line, SDA : Serial Data Line
Data Validity
A data on the SDA line is considered valid and stable only when the SCL signal is in HIGH state. The HIGH and
LOW states of the SDA line can only change when the SCL signal is LOW. Please refer to the figure below.
SDA
SCL
Data line
stable,
Data
change
Data valid allowed
Byte Format
Every byte transmitted to the SDA line consists of 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transmitted first.
Acknowledge
During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral
(audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that
the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below.
SCL
1
2
3
7
8
9
SDA
MSB
Acknowledge
Start
The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise,
the SDA line will remain at the HIGH level during the ninth (9th) clock pulse. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
REV1.0
7
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