欢迎访问ic37.com |
会员登录 免费注册
发布采购

M62320FP 参数 Datasheet PDF下载

M62320FP图片预览
型号: M62320FP
PDF下载: 下载PDF文件 查看货源
内容描述: 8位I / O扩展器I2C总线 [8-BIT I/O EXPANDER for I2C BUS]
分类和应用: 并行IO端口微控制器和处理器外围集成电路光电二极管
文件页数/大小: 9 页 / 68 K
品牌: MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
 浏览型号M62320FP的Datasheet PDF文件第1页浏览型号M62320FP的Datasheet PDF文件第2页浏览型号M62320FP的Datasheet PDF文件第3页浏览型号M62320FP的Datasheet PDF文件第4页浏览型号M62320FP的Datasheet PDF文件第5页浏览型号M62320FP的Datasheet PDF文件第6页浏览型号M62320FP的Datasheet PDF文件第8页浏览型号M62320FP的Datasheet PDF文件第9页  
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
8-BIT I/O EXPANDER for I C BUS
FUNCTIONAL DESCRIPTION
All parallel data I/O terminals are set to the input-state after power-on. In case any terminals need to be set to
the output state, the corresponding terminals should be set during the write mode. This setting is hold until a
next setting.
2
In the write mode, 8 bits data can be transmitted from the I C BUS interface to the parallel ports continually after
the slave address and I/O setting.
In the read mode, 8 bits data can be transmitted from the parallel ports to the I
2
C BUS interface continually after
the slave address setting.
In the case of a changing between the write- and read-mode, the data must be transmitted again from the
starting condition.
2
• In a case of a data conversion from serial to parallel.
Transmission from a master (MCU etc.)
Transmission from a slave (M62320)
starting
condition slave address
SDA
SCL
0
1
I/O setting byte
A
DATA
DATA
stop condition
1
2
1
3
1 A2 A1 A0 0
4
5
6
7
8
P7 P6 P5 P4 P3 P2 P1 P0 A D
1
7D
1
6 D
1
5 D
1
4 D
1
3D
1
2 D
1
1 D
1
0 A D
2
7D
2
6 D
2
5 D
2
4 D
2
3D
2
2 D
2
1 D
2
0 A
1
2
3
4
5
6
7
8
Data output
D0
to
D7
Data output
D
2
X
Hi-Z
D
1
X
• In a case of a data conversion from parallel to serial.
All I/O setting resistors are set to low (input) in the write mode, before a parallel data is read. (All I/O
setting resistors are set to the input mode after power-on.)
Transmission from a master (MCU etc.)
Transmission from a slave (M62320)
I/O setting byte
A
P7 P6 P5 P4 P3 P2 P1 P0 A
1
2
3
4
5
6
7
8
start
condition slave address
SDA
SCL
0
1
1
2
1
3
1 A2 A1 A0 0
4
5
6
7
8
D0 to D7
output
Hi-Z
start
condition slave address
SDA
SCL
0
1
stop condition
DATA
DATA
DATA
A D
1
7D
1
6 D
1
5 D
1
4 D
1
3D
1
2 D
1
1 D
1
0 A D
3
7 D
3
6 D
3
5 D
3
4 D
3
3 D
3
2 D
3
1 D
3
0 A D
4
7 D
4
6 D
4
5 D
4
4 D
4
3D
4
2 D
4
1 D
4
0 A
1
2
3
4
5
6
7
8
1
2
1
3
1 A2 A1 A0 1
4
5
6
7
8
D0 to D7
Input
(example)
D0 to D7
Output
D
1
X
D
2
X
D
3
X
D
4
X
data latch
Hi-Z
data latch
data latch
MITSUBISHI ELECTRIC
2/20,1998(rev) ( 7 / 9 )