'97.4.7
MITSUBISHI LSIs
M5M5256DP,KP,FP,VP,RV -45LL-I,-55LL-I,-70LL-I,
-45XL-I,-55XL-I,-70XL-I
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(1) MEASUREMENT CONDITIONS
(Ta = -40~85°C, Vcc=5V±10%, unless otherwise noted )
Vcc
1.8kΩ
DQ
990Ω
(Including
scope and JIG)
Input pulse level···················V
IH
=2.4V,V
IL
=0.6V
Input rise and fall time··········5ns
Reference level····················V
OH
=V
OL
=1.5V
Output loads·························Fig.1,CL=30pF (-45LL,-45XL )
CL=50pF (-55LL,-55XL )
CL=100pF (-70LL,-70XL )
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
C
L
Fig.1 Output load
(2) READ CYCLE
Symbol
t
CR
t
a
(A)
t
a
(S)
t
a
(OE)
t
dis
(S)
t
dis
(OE)
t
en
(S)
t
en
(OE)
t
V
(A)
Parameter
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after /S high
Output disable time after /OE high
Output enable time after /S low
Output enable time after /OE low
Data valid time after address
-45LL, XL
Min Max
45
45
45
25
15
15
5
5
10
Limits
-55LL, XL
Min Max
55
55
55
30
20
20
5
5
10
-70LL, XL
Min Max
70
70
70
35
25
25
5
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
-45LL, XL
Symbol
Parameter
Min Max
t
CW
45
Write cycle time
t
w
(W)
Write pulse width
35
t
su
(A)
Address setup time
0
t
su
(A-WH)
Address setup time with respect to /W high 40
t
su
(S)
Chip select setup time
40
t
su
(D)
Data setup time
20
t
h
(D)
Data hold time
0
t
rec
(W)
Write recovery time
0
t
dis
(W)
Output disable time from /W low
15
t
dis
(OE)
Output disable time from /OE high
15
t
en
(W)
Output enable time from /W high
5
t
en
(OE)
Output enable time from /OE low
5
Limits
-55LL, XL
Min Max
55
40
0
50
50
25
0
0
20
20
5
5
-70LL, XL
Min Max
70
50
0
65
65
30
0
0
25
25
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI
ELECTRIC
4
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
