MITSUBISHI MICROCOMPUTERS
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
●value of high-order 6-bit counter
WATCHDOG TIMER
●value of STP instruction disable bit
●value of count source selection bit.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software runaway).
When bit 6 of the watchdog timer control register (address 003716)
is set to “0,” the STP instruction is valid. The STP instruction is dis-
abled by rewriting this bit to “1.” At this time, if the STP instruction
is executed, it is processed as an undefined instruction, so that a
reset occurs inside.
The watchdog timer consists of an 8-bit watchdog timer L and a 6-
bit watchdog timer H. At reset or writing to the watchdog timer
control register (address 003716), the watchdog timer is set to
“3FFF16.” When any data is not written to the watchdog timer con-
trol register (address 003716) after reset, the watchdog timer is in
stop state. The watchdog timer starts to count down from “3FFF16”
by writing an optional value into the watchdog timer control regis-
ter (address 003716) and an internal reset occurs at an underflow.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 003716) may be
started before an underflow. The watchdog timer does not function
when an optional value have not written to the watchdog timer
control register (address 003716). When address 003716 is read,
the following values are read:
This bit cannot be rewritten to “0” by programming. This bit is “0”
immediately after reset.
The count source of the watchdog timer becomes the system
clock φ divided by 8. The detection time in this case is set to 8.19 s
at XCIN = 32 kHz and 65.536 ms at XIN = 4 MHz.
However, count source of high-order 6-bit timer can be connected
to a signal divided system clock by 8 directly by writing the bit 7 of
the watchdog timer control register (address 003716) to “1.” The
detection time in this case is set to 32 ms at XCIN = 32 kHz and
256 µs at XIN = 4 MHz. There is no difference in the detection time
between the middle-speed mode and the high-speed mode.
“FF16” is set when
watchdog timer is
Data bus
XCIN
Watchdog timer count
source selection bit
“0”
written to.
Watchdog timer
“1”
“0”
Internal
system clock
selection bit
L (8)
Watchdog timer
1/16
“1”
H (6)
“3F16” is set when
watchdog timer is
written to.
XIN
Undefined instruction
Reset
STP instruction disable bit
STP instruction
Internal reset
Reset circuit
RESETIN
Reset release time wait
Fig. 44 Block diagram of watchdog timer
b7
b0
Watchdog timer register (address 003716
)
WDTCON
Watchdog timer H (for read-out of high-order 6 bit)
“3FFF16” is set to the watchdog timer by writing values to this address.
STP instruction disable bit
0
STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Internal system clock/2048 (f(XIN)/4096)
1 : Internal system clock/8 (f(XIN)/16)
Fig. 45 Structure of watchdog timer control register
f(XIN)
Internal
reset signal
2ms (f(XIN) = 4MHZ)
Watchdog timer detection
Fig. 46 Timing of reset output
41
MITSUBISHI [ Mitsubishi Group ]
