MITSUBISHI MICROCOMPUTERS
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ment/output port pins are pulled up to the VCC (=VL3) voltage in
the high impedance condition. The segment/I/O port pins are set
to input ports, and VCC (=VL3) is applied to them by pull-up resis-
tor.
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
LCD Display RAM
When releasing from reset, the VCC (VL3) voltage is output from
the common pins.
Address 004016 to 005316 is the designated RAM for the LCD dis-
play. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
Table 9 Duty ratio control and common pins used
Duty ratio selection bit
Duty
LCD Drive Timing
Common pins used
ratio
Bit 1
Bit 0
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the
following equation;
2
3
4
0
1
1
1
0
1
COM0, COM1 (Note 1)
COM0–COM2 (Note 2)
COM0–COM3
(frequency of count source for LCDCK)
f(LCDCK) =
Notes1: COM2 and COM3 are open.
2: COM3 is open.
(divider division ratio for LCD)
f(LCDCK)
Frame frequency =
(duty ratio)
Segment Signal Output Pin
Segment signal output pins are classified into the segment-only
pins (SEG0–SEG17), the segment/output port pins (SEG18–
SEG25), and the segment/I/O port pins (SEG26–SEG39).
Segment signals are output according to the bit data of the LCD
RAM corresponding to the duty ratio. After reset release, a VCC
(=VL3) voltage is output to the segment-only pins and the seg-
Bit
7
6
5
4
3
2
1
0
address
004016
004116
004216
004316
004416
004516
004616
SEG
SEG
SEG
SEG
SEG
0
2
4
6
8
SEG
1
3
5
7
9
SEG
SEG
SEG
SEG
SEG10
SEG11
SEG13
SEG15
SEG17
SEG19
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
SEG33
SEG35
SEG37
SEG39
SEG30
SEG32
SEG34
SEG36
SEG38
COM
3
COM
2
COM
1
COM
0
COM
3
COM
2
COM
1
COM0
Fig. 41 LCD display RAM map
38