M37211M2-011SP 参数 Datasheet PDF下载

型号：	M37211M2-011SP
PDF下载：	下载PDF文件查看货源
内容描述：	单片8位微机的CMOS电压合成器与屏幕上的显示控制器 [SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER]
分类和应用：	显示控制器计算机
文件页数/大小：	59 页 / 760 K
品牌：	MITSUBISHI [ Mitsubishi Group ]

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

FUNCTIONS

Parameter

Functions

Number of basic instructions

Instruction execution time

Clock frequency

0.5µs (the minimum instruction execution time, at 8MHz oscillation frequency)

8MHz

12 K bytes

ROM

RAM

ROM

RAM

ROM

RAM

I/O

M37210M3-XXXSP/FP

M37210M4-XXXSP

M37211M2-XXXSP

256 bytes

16 K bytes

Memory size

320 bytes

8 K bytes

192 bytes

8-bit ✕ 1 (can be used as N-channel open-drain output and PWM4-PWM7)(Note)

P10 – P14

P15 – P17

5-bit

3-bit

8-bit

2-bit

1 (CMOS 3-state output)

1 (can be used as A-D input)

1 (CMOS 3-state output)

1 (CMOS 3-state input/output)

I/O

Input

I/O

P30, P31

P32, P35

P40, P41

P42

I/O

Input/Output ports

4-bit

2-bit

1 (can be used as timer input pins, INT input pins and A-D input pins)

1 (can be used as N-channel open-drain output and serial I/O function pins)

Input

I/O

1-bit

4-bit

1 (can be used as serial I/O and A-D input)

Input

Output

✕ 1 (can be used as R, G, B, OUT pins)

4-bit ✕ 1 (can be used as N-channel open-drain output and PWM0-PWM3 output pins)

Serial I/O

8-bit ✕ 1

Timers

8-bit timer ✕ 4

Subroutine nesting

96 levels (max.)

Two external interrupts, four internal timer interrupts,

one serial I/O interrupt, one CRT interrupt, one f(XIN)/4096

interrupt, one VSYNC interrupt, BRK instruction

Interrupt

Clock generating circuit

Power source voltage

Built-in circuit (externally connected a ceramic resonator or a quartz-crystal oscillator)

5V ± 10%

at CRT display ON

at CRT display OFF

at stop mode

110mW (at 4MHz oscillation frequency, VCC = 5.5V, Typ.)

55mW (at 4MHz oscillation frequency, VCC = 5.5V, Typ.)

1.65mW (Max.)

Power dissipation

Operating temperature range

Device structure

−10 to 70°C

CMOS silicon gate process

M37210M3-XXXSP, M37210M4-XXXSP, M37211M2-XXXSP 52-pin shrink plastic molded DIP

Package

M37210M3-XXXFP

64-pin plastic molded QFP

Number of character

Character dot construction

Kinds of characters

18 characters ✕ 2 lines : maximum 16 lines (by software)

12 ✕ 16 dots

96 kinds

CRT display function

Character size

3 kinds

Kinds of color

7 kinds max, (R, G, B) : can be specified by character unit

64 levels (horizontal) ✕ 128 levels (vertical)

Display position (horizontal, vertical)

Note : The M37211M2-XXXSP can be also used as PWM4 and PWM5.

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

PIN DESCRIPTION

Input /

Output

Name

Functions

VCC,

Power source voltage

Apply voltage of 5V ± 10% to VCC, and 0V to VSS.

VSS

CNVSS

RESET

CNVSS

This is connected to VSS.

Reset input

Input

To enter the reset state, the reset input pin must be kept at a “L” for 2µs or more (under nor-

mal VCC conditions).

If more time is needed for the crystal oscillator to stabilize, this “L” condition should be main-

tained for the required time.

XIN

Clock input

Input

This chip has an internal clock generating circuit.To control generating frequency, an exter-

nal ceramic resonator or a quartz-crystal oscillator is connected between the XIN and

XOUT pins. If an external clock is used, the clock source should be connected the XIN pin and

the XOUT pin should be left open.

XOUT

Clock output

Output

Timing output

I/O port P0

Output This is the timing output pin.

P00 – P07

I/O

Port P0 is an 8-bit I/O port with directional registers allowing each I/O bit to be individually

programmed as input or output. At reset, this port is set to input mode. The output structure

is CMOS output.

The output structure is N-channel open-drain output. When PWM4, PWM5, PWM6 and

PWM7 are used, P00, P01, P02 and P03 are in common with PWM output pins of PWM4,

PWM5, PWM6 and PWM7.

P11 – P14

I/O port P1

I/O

Input

I/O

Ports P10, P11, P12, P13 and P14 are 5-bit I/O ports and have basically the same functions

as port P0. The output structure is CMOS output.

P15 – P17 Input port P1

Ports P15, P16 and P17 are 3-bit input ports and they are in common with input pins of A-D

comparator (A-D1, A-D2 and A-D3).

P20 – P27

P30, P31

I/O port P2

I/O port P3

Port P2 is an 8-bit I/O port and has basically the same functions as port P0.

The output structure is CMOS output.

I/O

Ports P30 and P31 are 2-bit I/O ports and have basically the same functions as port P0.

The output structure is CMOS output.

P32 – P35 Input port P3

Input

Ports P32, P33, P34 and P35 are 4-bit input ports and ports P32 and P33 are in common

with external clock input pins of timers 2 and 3. Ports P34 and P35 are in common with

external interrupt input pins INT1 and INT2. Port P35 is in common with an input pin of A-D

comparator (A-D4).

P40, P41

P42

I/O port P4

I/O

Ports P40 and P41 are 2-bit I/O ports and have basically the same functions as port P0.

When serial I/O is used, ports P40 and P41 are in common with SOUT pin and SCLK pin, re-

spectively.

Input port P4

Input

Port P42 is an 1-bit Input port, and it is common with an input pin of A-D comparator (A-D5)

and serial input pin (SIN).

P60 – P63 Output port P6

Output Port P6 is an 4-bit output port. The output structure is N-channel open-drain. This port is in

common with 6-bit PWM output pins PWM0-PWM3.

OSC1,

OSC2

Clock input for CRT

display

Input

Output

This is the I/O pins of the clock generating circuit for the CRT display function.

Clock output for CRT

display

HSYNC

VSYNC

HSYNC input

VSYNC input

CRT output

Input

This is the horizontal synchronizing signal input for CRT display.

This is the vertical synchronizing signal input for CRT display.

R, G, B,

OUT

Output This is a 4-bit output pin for CRT display. The output structure is CMOS output. This is in

common with port P52 – P55.

D-A

DA Output

Output This is an output pin for 14-bit PWM.

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

FUNCTIONAL DESCRIPTION

CPU Mode Register

Central Processing Unit (CPU)

The CPU mode register is allocated at address 00FB16. The CPU

The M37210M3-XXXSP/FP uses the standard 740 family instruction

set. Refer to the table of 740 family addressing modes and machine

instructions or the SERIES 740 Software User’s Manual for details

on the instruction set.

mode register contains the stack page selection bit.

Machine-resident 740 family instructions are as follows :

The FST and SLW instruction cannot be used.

The MUL, DIV, WIT, and STP instruction can be used.

CPU mode register

(CPUM : address 00FB16)

Fix these bits to “002”

Stack page selection bit (Note)

0 : Zero page

1 : 1 page

Fix these bits to “11112”

Note : Please beware of this bit when programming because it is set to “1” after the reset release.

Especially the internal RAM of the M37211M2-XXXSP is in the zero page, so be sure to set this bit to “0”.

Fig. 1 Structure of CPU mode register

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

MEMORY

Interrupt Vector Area

Special Function Register (SFR) Area

The special function register (SFR) area in the zero page contains

control registers such as I/O ports and timers.

The interrupt vector area contains reset and interrupt vectors.

Zero Page

The 256 bytes from addresses 000016 to 00FF16 are called the zero

page area. The internal RAM and the special function registers

(SFR) are allocated to this area.

RAM

RAM is used for data storage and for stack area of subroutine calls

and interrupts.

The zero page addressing mode can be used to specify memory and

only 2 bytes is possible in the zero page addressing mode.

ROM

ROM is used for sroring user programs as well as the interrupt vec-

tor area.

Special Page

The 256 bytes from addresses FF0016 to FFFF16 are called the spe-

cial page area. The special page addressing mode can be used to

specify memory addresses in the special page area. Access to this

area with only 2 bytes is possible in the special page addressing

mode.

RAM for Display

RAM for display is used for specifing the character codes and colors

to display.

ROM for Display

ROM for display is used for storing character data.

000016

RAM

(192 bytes)

for

M37211M2

RAM

(256 bytes)

for

Zero page

00BF16

00FF16

RAM

(320 bytes)

for

SFR area

M37210M3

M37210M4

013F16

017F16

Not used

200016

20B116

RAM for display (Note)

(72 bytes)

300016

35FF16

Not used

ROM for display

(3 K bytes)

380016

3DFF16

C00016

D00016

E00016

ROM

(16 K bytes)

for

ROM

(12 K bytes)

for

ROM

(8 K bytes)

for

M37210M4

FF0016

M37210M3

M37211M2

Special page

FFDE16

FFFF16

Interrupt vector area

Note : Refer to Table 6. Contents of CRT display RAM

Fig. 2 Memory map

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

Port P0

Port P0 directional register

Port P1

Port P1 directional register

Port P2

Port P2 directional register

Port P3

Port P3 directional register

Port P4

Port P4 directional register

Port P5

Port P5 control register

Port P6

Port P6 directional register

14DA-H register

14DA-L register

PWM0 register

PWM1 register

PWM2 register

PWM3 register

PWM4 register

PWM output control register 1

PWM output control register 2

Horizontal position register

00E116 Vertical position register 1 (block 1)

00C016

00C116

00C216

00C316

00C416

00C516

00C616

00C716

00C816

00C916

00CA16

00CB16

00CC16

00CD16

00CE16

00CF16

00D016

00D116

00D216

00D316

00D416

00D516

00D616

00D716

00D816

00D916

00DA16

00DB16

00DC16

00DD16

00DE16

00DF16

00E016

Vertical position register 2 (block 2)

00E216

00E316

00E416

00E516

00E616

00E716

00E816

00E916

00EA16

00EB16

00EC16

00ED16

00EE16

00EF16

00F016

00F116

00F216

00F316

00F416

00F516

00F616

00F716

00F816

00F916

00FA16

00FB16

00FC16

00FD16

00FE16

00FF16

Character size register

Border selection register

Color register 0

Color register 1

Color register 2

Color register 3

CRT control register

CRT port control register

A-D mode register

A-D control register

Timer 1

Timer 2

Timer 3

Timer 4

Timer 12 mode register

Timer 34 mode register

PWM5 register

PWM6 register (Note)

PWM7 register (Note)

Interrupt

determination register

Interval

Interrupt Interval determination control register

mode register

CPU

Serial I/O mode register

Serial I/O register

Interrupt request register 1

Interrupt request register 2

Interrupt control register1

Interrupt control register2

Note : The M37211M2-XXXSP dose not have this register

Fig. 3 Memory map of special function register (SFR )

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

INTERRUPTS

All interrupts except the BRK instruction interrupt have an interrupt

request bit and an interrupt enable bit. The interrupt request bits are

in interrupt request registers 1 and 2 and the interrupt enable bits are

in interrupt control registers 1 and 2. Figure 4 shows the structure of

the interrupt request registers 1 and 2 and interrupt control registers

1 and 2.

Interrupts can be caused by 12 different sources consisting of 3 ex-

ternal, 7 internal, 1 software, and reset.

Interrupts are vectored interrupts with priorities shown in Table 1. Re-

set is also included in the table because its operation is similar to an

interrupt.

When an interrupt is accepted, the registers are pushed, interrupt

disable flag I is set, and the program jumps to the address specified

in the vector table. The interrupt request bit is cleared automatically.

The reset can never be disabled. Other interrupts are disabled when

the interrupt disable flag is set.

Interrupts other than the BRK instruction interrupt and reset are ac-

cepted when the interrupt enable bit is “1”, interrupt request bit is “1”,

and the interrupt disable flag is “0”. The interrupt request bit can be

reset with a program, but not set. The interrupt enable bit can be set

and reset with a program.

Reset is treated as a non-maskable interrupt with the highest priority.

Figure 5 shows interrupts control.

Table 1. Interrupt vector addresses and priority

Interrupt sources

Priority

Vector addresses

Remarks

Reset

FFFF16, FFFE16

FFFD16, FFFC16

FFFB16, FFFA16

FFF916, FFF816

FFF516, FFF416

FFF316, FFF216

FFF116, FFF016

FFEF16, FFEE16

FFED16, FFEC16

FFEB16, FFEA16

FFE916, FFE816

FFDF16, FFDE16

Non-maskable

CRT interrupt

INT2 interrupt

Active edge selectable

INT1 interrupt

Timer 4 interrupt

f(XIN)/4096 interrupt

VSYNC interrupt

Timer 3 interrupt

Timer 2 interrupt

Timer 1 interrupt

Serial I/O interrupt

BRK instruction interrupt

Active edge selectable

Non-maskable software interrupt

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

Interrupt request register 1

Interrupt request register 2

(IREQ2 : address 00FD16)

(IREQ1 : address 00FC16

)

Timer 1 interrupt request bit

Timer 2 interrupt request bit

Timer 3 interrupt request bit

Timer 4 interrupt request bit

CRT interrupt request bit

INT

interrupt request bit

Serial I/O1 interrupt request bit

f(XIN)/4096 interrupt request bit

Fix this bit to “0”

SYNC interrupt request bit

0 : No interrupt request issued

1 : Interrupt request issued

0 0

Interrupt control register 1

Interrupt control register 2

(ICON2 : address 00FF16)

(ICON1 : address 00FE16

)

Timer 1 interrupt enable bit

Timer 2 interrupt enable bit

Timer 3 interrupt enable bit

Timer 4 interrupt enable bit

CRT interrupt enable bit

INT

interrupt enable bit

Serial I/O1 interrupt enable bit

Fix this bit to “0”

f(XIN)/4096 interrupt enable bit

Fix these bits to “0”

SYNC interrupt enable bit

Fix these bits to “0”

0 : Interrupt disabled

1 : Interrupt enabled

Fig. 4 Structure of interrupt-related registers

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

BRK instruction

reset

interrupt request

Fig. 5 Interrupt control

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

Data bus

Timer 1 latch (8)

1/4096

Timer 1

interrupt request

Timer 1 (8)

XIN

1/2

1/8

T12M0

T12M4

T12M2

Timer 2 latch (8)

Timer 2

Timer 2 (8)

P32/TIM2

D.F.

interrupt request

T12M1

T12M3

HSYNC

Reset

STP instruction

FF16

Timer 3 latch (8)

P33/TIM3

D.F.

T34M5

Timer 3

interrupt request

Timer 3 (8)

T34M0

T34M2

0716

Timer 4 latch (8)

T34M1

Timer 4

interrupt request

Timer 4 (8)

T34M4

T34M3

Selection gate : Connected to black

colored side at reset.

T12M : Timer 12 mode register

T34M : Timer 34 mode register

Notes 1 : “H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.

2 : When the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal.

3 : In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.

Fig. 7 Timer block diagram

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

SERIAL I/O

Bit 3 decides whether parts of P4 will be used as a serial I/O or not.

To use P42 as a serial input, set the directional register bit which cor-

responds to P42 to “0”. For more information on the directional regis-

ter, refer to the I/O pin section.

M37210M3-XXXSP has a serial I/O.

A block diagram of the serial I/O is shown in Figure 8.

Synchronous input/output clock (SCLK), and the serial I/O pins (SOUT,

SIN) are used as port P4. The serial I/O mode registers (address

00DC16) are 8-bit registers. Bits 0, 1 and 2 of these registers are

used to select a synchronous clock source.

The serial I/O function is discussed below. The function of the serial

I/O differs depending on the clock source ; external clock or internal

clock.

Data bus

Frequency

divider

XIN

1/2

1/4 1/8 1/16

SM1

SM2

SM0

Synchronization

circuit

P41 latch

Serial I/O

interrupt request

Serial I/O counter (8)

P41/SCLK

SM3

P40 latch

↔

SM5 : LSB MSB

P40/SOUT

P42/SIN

SM3

SM6

Serial I/O shift register (8)

(address 00DD16)

Selection gate : Connected to black

colored side at reset.

Fig. 8 Serial I/O block diagram

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

The serial I/O counter is set to 7 when data is stored in the serial I/O

put to SOUT. During the rising edge of this clock, data can be input

from SIN and the data in the serial I/O register will be shifted 1 bit.

Transfer direction can be selected by bit 5 of serial I/O mode register.

After the transfer clock has counted 8 times, the serial I/O register will

be empty and the transfer clock will remain at a high level. At this time

the interrupt request bit will be set.

of 50%. The timing diagram is shown in Figure 9. When using an ex-

ternal clock for transfer, the external clock must be held at “H” level

when the serial I/O counter is initialized. When switching between the

internal clock and external clock, the switching must not be per-

formed during transfer. Also, the serial I/O counter must be initialized

after switching.

Notes 1: On programming, note that the serial I/O counter is set by

writing to the serial I/O register with the bit managing in-

structions as SEB and CLB instructions.

External clock- If an external clock is used, the interrupt request will

be sent after the transfer clock has counted 8 times but transfer clock

will not stop.

2: When an external clock is used as the synchronizing clock,

write transmit data to the serial I/O register at “H” of the

transfer clock input level.

Due to this reason, the external clock must be controlled from the

outside. The external clock should not exceed 1MHz at a duty cycle

Sync. clock

Transfer clock

Serial I/O register

write signal

(Note 1)

Serial I/O output

SOUT

Serial I/O input

SIN

Interrupt request bit set

Notes 1 : If internal clock is selected, the Sout pin is at high impedance after transfer is completed.

2 : When an external clock is used as the synchronous clock, write the transmit data to the

serial I/O shift register at “H” of the transfer clock input level.

Fig. 9 Serial I/O timing (for LSB first)

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with ON-SCREEN DISPLAY CONTROLLER

Serial I/O common transmission/reception mode.

Write 1 to bit 6 of serial I/O mode register, and signals SIN and SOUT

switch internal to be able to serial data transmission/reception.

Figure 11 shows signals on serial I/O common transmission/recep-

tion mode.

Serial l/O mode register

(SM : address 00DC16)

Internal synchronous clock

selection bits

00 : f (XIN) /4

01 : f (XIN) /16

Note : Receive the serial data after writing “FF16” to the serial I/O

10 : f (XIN) /32

11 : f (XIN) /64

Synchronous clock selection bit

0 : External clock

1 : Internal clock

Serial l/O port selection bit

0 : P40, P41

1 : SOUT1,SCLK signal output pins

Fix this bit to “0”

Transfer direction selection bit

0 : LSB first

1 : MSB first

Serial input pin selection bit

0 : Input from SIN pin

1 : Input from SOUT pin

Fig. 10 Structure of serial I/O mode register

P41/SCLK

clock1

Input or output

The transmission mode

P40/SOUT (/IN)

“1”

“0”

Serial I/O shift register

SM6

The reception mode

P42/SIN

Port P42 data

Fig. 11 Signals on serial I/O common transmission/reception mode

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with ON-SCREEN DISPLAY CONTROLLER

PWM OUTPUT CIRCUIT

within one period in the circuit internal section. Refer to Figure

13 (a).

(1) Introduction

Six different pulses can be output from the PWM.

The M37210M3-XXXSP/FP and M37210M4-XXXSP are

equipped with one 14-bit PWM (DA) and eight 6-bit PWMs

(PWM0-PWM7), and the M37211M2-XXXSP is equipped with

six 6-bit PWMs (PWM0-PWM5).The 14-bit resolution gives DA

the minimum resolution bit width of 500ns (for f(XIN) = 4MHz)

and a repeat period of 8192µs. PWM0-PWM7 have a 6-bit reso-

lution with minimum resolution bit width of 16ms and repeat pe-

riod of 1024µs.

These can be selected by bits 0 through 5. Depending on the

content of the 6-bit PWM latch, pulses from 5 to 0 are selected.

The PWM output is the difference of the sum of each of these

pulses. Several examples are shown in Figure 13 (b). Changes

in the contents of the PWM latch allows the selection of 64

lengths of high-level area outputs varying from 0/64 to 63/64. A

length of entirely high-level output cannot be output, i.e. 64/64.

Block diagram of the PWM is shown in Figure 16.

The PWM timing generator section applies individual control

signals to DA and PWM0-7 using clock input XIN divided by 2

as a reference signal.

(5) 14-bit PWM Operation

The output example of the 14-bit PWM is shown in Figure 14.

The 14-bit PWM divides the data within the PWM latch into the

lower 6 bits and higher 8 bits.

A high-level area within a length DH times τ is output every short

area of t = 256 τ =128µs as determined by data DH of the higher

8 bits.

(2) Data Setting

The output pins PWM0-3 are in common with port P6 and

PWM4-7 are in common with port P00-P03.

Thus, the time for the high-level area is equal to the time set by

the lower 8 bits or that plus τ. As a result, the short-area period

t ( = 128µs, approx. 7.8 kHz) becomes an approximately repeti-

tive period.

For PWM output, each PWM output selection bit (bit 1 to 7 of

PWM output control register 1, bit 0, 1 of PWM output control

the higher 8-bit of the DA-H register (address 00CE16), then the

lower 6-bit of the DA-L register (address 00CF16).

When one of the PWM0-7 is used for output, set the 6-bit in the

PWM0-7 register (address 00D016 to 00D416, 00F616 to

00F816), respectively.

(6) Output after Reset

At reset the output of port P6 is in the high impedance state and

the contents of the PWM register and latch are undefined. Note

that after setting the PWM register, its data is transferred to the

latch.

(3) Transferring Data from Registers to PWM

Circuit

Table 2. Relation between the low-order 6 bits of data and high-level

area increase space

The data written to the PWM registers. 8 bits of the DA-H regis-

ter is transferred to 14-bit PWM circuit when writing to lower 6

bits of the DA-L register.

6 low-order bits of data Area longer by τ than that of other tm (m = 0 to 63)

0 0 0 0 0^L0^SB

0 0 0 0 0 1

Nothing

m = 32

(4) Operation of the 6-bit PWMs

0 0 0 0 1 0

0 0 0 1 0 0

0 0 1 0 0 0

0 1 0 0 0 0

1 0 0 0 0 0

m = 16, 48

The timing diagram of the eight 6-bit PWMs (PWM0-7) is shown

m = 8, 24, 40, 56

m = 4, 12, 20, 28, 36, 44, 52, 60

in Figure 13. One period (T) is composed of 64 (2 ) segments.

There are six different pulse types configured from bits 0 to 5

representing the significance of each bit. These are output

m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62

m = 1, 3, 5, 7, ................................................... 57, 59, 61, 63

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

Data bus

Selection gate : connected to black

colored side at reset.

DA-H register

(address 00CE16

)

Pass gate

bit 7

bit 0

DA-L register

(14-bit)

(address 00CF16

)

MSB

LSB

PN2

PN4

14-bit PWM circuit

D-A

PW1

Timing

generator

for PWM

XIN

1/2

PW0

PWM0 register

(address 00D016

)

bit 0

bit 5

P60 D60

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PN3

6-bit PWM circuit

PW2

P61 D61

PW3

P62 D62

PW4

P63 D63

PW5

P00 D00

PW6

P01 D01

PW7

P02 D02

PWM6(Note)

PWM7(Note)

PN0

P03 D03

PN1

PW : PWM output control register 1

PN : PWM output control register 2

D0 : Port P0 direction register

P0 : Port P0

Note : The M37211M2-XXXSP can not output the PWM.

Inside of

is as same contents with the others.

D6 : Port P6 directional register

P6 : Port P6

Fig. 12 PWM block diagram

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

PWM output control register 1

(PW : address 00D516)

PWM output control register 2

(PN : address 00D616)

DA, PWM count source STOP bit

0 : Supply

1 : Stop

P02/PWM6 output selection bit (Note)

0 : P02 (general-purpose) output

1 : PWM6 (6-bit PWM) output

DA/PN4 output selection bit

0 : DA (14-bit PWM) output

1 : PN4 (general-purpose) output

P03/PWM7 output selection bit (Note)

0 : P03(general-purpose) output

1 : PWM7 (6-bit PWM) output

P60/PWM0 output selection bit

0 : P60 (general-purpose) output

1 : PWM0 (6-bit PWM) output

DA output polarity selection bit

0 : Positive polarity

1 : Negative polarity

P61/PWM1 output selection bit

0 : P61 (general-purpose) output

1 : PWM1 (6-bit PWM) output

6-bit PWM output polarity selection bit

0 : Positive polarity

1 : Negative polarity

P62/PWM2 output selection bit

0 : P62 (general-purpose) output

1 : PWM2 (6-bit PWM) output

D-A pin general-purpose output register

0 : Output “L”

1 : Output “H”

P63/PWM3 output selection bit

0 : P63 (general-purpose) output

1 : PWM3 (6-bit PWM) output

P00/PWM4 output selection bit

0 : P00 (general-purpose) output

1 : PWM4 (6-bit PWM) output

P01/PWM5 output selection bit

0 : P01 (general-purpose) output

1 : PWM5 (6-bit PWM) output

Note : Fix this bit to “0” (M37211M2-XXXSP).

Fig.15 Structure of PWM output control registers 1 and 2

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

A-D COMPARATOR

Block diagram of A-D comparator is shown in Figure 18. A-D com-

parator consists of 5-bit D-A converter and comparator.The A-D con-

trol register can generate 1/64 VCC-step internal analog voltage

based on the settings of bits 0 to 4.

A-D control register

(ADC : address 00EF16)

D-A converter set bits

(refer to table 3)

Table 3 gives the relation between the descriptions of A-D control

comparison result of the analog input voltage and the internal analog

voltage is stored in the A-D control register, bit 5.

Strage bit of comparison result

0 : Input voltage <

reference voltage

1 : Input voltage >

After selection of an analog input pin by bits 0-2 of A-D mode register

(address 00EE16), the digital value corresponding to the internal ana-

log voltage to be compared is then written in the A-D control register,

bit 0 to 3 and an analog input pin is selected. After 16 machine cycle,

the voltage comparison is completed.

reference voltage

Fig. 16 Structure of A-D control register

Table 3. Relationship between the contents of A-D control register

and reference voltage

A-D control register

Reference voltage Vref

Bit4

Bit 3 Bit 2 Bit 1 Bit 0

1/64 VCC

3/64 VCC

5/64 VCC

A-D mode regiser

(ADM : address 00EE16)

A-D input pin selection bits

0 0 0 : A-D1

0 0 1 : A-D2

0 1 0 : A-D3

0 1 1 : A-D4

1 0 0 : A-D5

1 0 1 :

27/64 VCC

29/64 VCC

31/64 VCC

These are not

1 1 0 :

available

1 1 1 :

Fig. 17 Structure of A-D mode register

Data bus

Comparator control

Comparator

A-D mode register

Bits 0 to 2

A-D control register

P15/A-D1

Analog

signal

switch

P16/A-D2

P17/A-D3

P35/A-D4

P42/A-D5

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Switch tree

Resistor ladder

Fig. 18 A-D comparator block diagram

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

CRT DISPLAY FUNCTIONS

➀

➁

Set the character to be displayed in display RAM.

Set the display color by using the color register.

➂ Specify the color register in which the display color is set by us-

ing the display RAM.

(1) Outline of CRT Display Functions

Table 4 outlines the CRT display functions of the M37210M3-XXXSP.

The M37210M3-XXXSP incorporates a 18 columns ✕ 2 lines CRT

display control circuit. CRT display is controlled by the CRT display

control register.

➃ Specify the vertical position and character size by using the verti-

cal position register and the character size register.

➄ Specify the horizontal position by using the horizontal position

Up to 96 kinds of characters can be displayed, and colors can be

specified for each character. Four colors can be displayed on one

screen. A combination of up to 7 colors can be obtained by using

each output signal (R, G and B).

➅ Write the display enable bit to the designated block display flag of

the CRT control register. When this is done, the CRT starts op-

eration according to the input of the VSYNC signal.

The CRT display circuit has an extended display mode.

This mode allows multiple lines (more than 3 lines) to be displayed

on the screen by interrupting the display each time one line is dis-

played and rewriting data in the block for which display is terminated

by software.

Characters are displayed in a 12 ✕ 16 dot configuration to obtain

smooth character patterns (refer to Figure 19).

The following shows the procedure how to display characters on the

CRT screen.

Figure 21 shows a block diagram of the CRT display control circuit.

Figure 20 shows the structure of the CRT display control register.

Table 4. Outline of CRT display functions

Parameter

Functions

Number of display

character

18 characters ✕ 2 lines

Character

configuration

12 ✕ 16 dots (refer to Figure 19)

Kinds of character

Character size

CRT control register

(CC : address 00EA16)

3 kinds

Kinds of color

Color

1 screen : 4 kinds

A character

Display of all blocks control bit (Note)

0 : Display of all blocks off

1 : Display of all blocks on

Coloring unit

Display expansion

Raster coloring

Possible (multiline display)

Possible (maximum 7 kinds)

Display of block 1 control bit

0 : Display of block 1 off

1 : Display of block 1 on

12 dots

Display of block 2 control bit

0 : Display of block 2 off

1 : Display of block 2 on

Note : Display is controlled by logical product (AND) between the all-

blocks display control bit and each block display control bit

Fig. 20 Structure of CRT control register

16 dots

Fig. 19 CRT display character configuration

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

OSC1

OSC2

HSYNC

SYNC

(Address 00EA16

)

CRT control register

Display oscillation

circuit

(Addresses 00E116 to 00E216)

Vertical position registers

(Address 00E416

Character size register

(Address 00E016

Horizontal position register

(Address 00E516

)

Display position control circuit

)

Border selection register

Display control

circuit

RAM for display

9 bits × 18 × 2

ROM for display

12 bits 16 96

(Addresses 00E616

to 00E916

)

Shift register

12 bits

Shift register

12 bits

Color registers

(Address 00EC16

)

Output circuit

CRT port control register

Data bus

OUT

Fig. 21 Block diagram of CRT display control circuit

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

(2) Display Position

The display positions of characters are specified in units called a

“block”. There are two blocks, block 1 and block 2.

Up to 18 characters can be displayed in one block (refer to (4)

Memory for Display).

The display position of each block in both horizontal and vertical di-

rections can be set by software.

The horizontal direction is common to all blocks, and is selected from

64-step display positions in units of 4Tc (Tc = oscillating cycle for dis-

play).

The display position in the vertical direction is selected from 128-step

display positions for each block in units of four scanning lines.

Block 2 is displayed after the display of block 1 perfectly (fig. 24(a)).

Then if the display of block 2 starts during the display of block 1, only

block 1 is displayed. As same, when multiline display, block 1 is dis-

played after the display of block 2 perfectly (fig. 24(b)).

The vertical position can be specified from 128-step positions (four

scanning lines per step) for each block by setting values 0016 to 7F16

to bits 0 to 6 in the vertical position register (addresses 00E116 and

00E215). Figure 22 shows the structure of the vertical position regis-

ter.

Vertical position registers 1, 2

(CV1 : address 00E116)

(CV2 : address 00E216)

The vertical display start positions

128-step positions (0016 to 7F16)

Fig. 22 Structure of vertical position registers

The horizontal direction is common to all blocks, and can be speci-

fied from 64-step display positions (4Tc per step (Tc = oscillating

cycle for display) by setting values 0016 to 3F16 to bits 0 to 5 in the

horizontal position register (address 00E016). Figure 23 shows the

structure of the horizontal position register.

Horizontal position register

(HR : address 00E016)

The horizontal display start positions

64-step positions (0016 to 3F16)

Fig. 23 Structure of horizontal position register

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

(RH)

CV1

Block 1

Block 2

CV2

(a) Example when each block is separated

CV1

Block 1

CV2

No display

Block 2

CV1

Block 1 (second)

(b) Example when block 2 overlaps with block 1

Fig. 24 Display position

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

(3) Character Size

The size of characters to be displayed can be selected from three

sizes for each block. Use the character size register (address

00E416) to set a character size. The character size in block 1 can be

specified by using bits 0 and 1 in the character size register ; the

character size in block 2 can be specified by using bits 2 and 3. Fig-

ure 25 shows the structure of the character size register.

Character size register

(CS : address 00E416)

Character size of block 1 selection bits

00 : Minimum size

01 : Medium size

The character size can be selected from three sizes : small size, me-

dium size and large size. Each character size is determined by the

number of scanning lines in the height (vertical) direction and the

cycle of display oscillation ( = Tc) in the width (horizontal) direction.

The small size consists of [one scanning line] ✕ [1 Tc] ; the medium

size consists of [two scanning lines] ✕ [2 Tc] ; and the large size con-

sists of [three scanning lines] ✕ [3 Tc].

10 : Large size

11 : This is not available

Character size of block 2 selection bits

00 : Minimum size

01 : Medium size

10 : Large size

11 : This is not available

Table 5 shows the relationship between the set values in the charac-

ter size register and the character sizes.

Fig. 25 Structure of character size register

Table 5. The relationship between the set values of the character size register and the character sizes

Set values of the character size register

Character

size

Width (horizontal) direction

Tc : oscillating cycle for display

Height (vertical) direction

scanning lines

CSn1

CSn0

Minimum

Medium

Large

1Tc

2Tc

3Tc

This is not available

Note : The display start position in the horizontal direction is not affected by the character size. In other words, the horizontal display start position is common to

all blocks even when the character size varies with each block (refer to Figure 26).

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

The CRT display ROM has a capacity of 3K bytes. Because 32 bytes

(4) Memory for Display

are required for one character data, the ROM can contain up to 96

kinds of characters.

There are two types of memory for display : ROM of CRT display (ad-

dresses 300016 to 35FF16, 380016 to 3DFF16) used to store charac-

ter dot data (masked) and display RAM (addresses 200016 to

20B116) used to specify the colors of characters to be displayed.The

following describes each type of display memory.

The CRT display ROM space is broadly divided into two areas. The

[vertical 16 dots] × [horizontal (left side) 8 dots] data of display char-

acters are stored in addresses 300016 to 35FF16 ; the [vertical 16

dots] × [horizontal (right side) 4 dots] data of display characters are

stored in addresses 380016 to 3DFF16 (refer to Figure 27). Note how-

ever that the four upper bits in the data to be written to addresses

380016 to 3DFF16 must be set to “1” (by writing data F016 to FF16).

➀ ROM for display (addresses 300016 to 35FF16 and 380016 to

3DFF16)

The CRT display ROM contains dot pattern data for characters to be

displayed. For characters stored in this ROM to be actually dis-

played, it is necessary to specify them by writing the character code

inherent to each character (code determined based on the ad-

dresses in the CRT display ROM) into the CRT display RAM.

Table 6. Character code list

Contained up address of character data

Character code

Left 8 dots lines

Right 4 dots lines

300016

300F16

380016

380F16

0016

0116

0216

Minimum

301016

301F16

381016

381F16

302016

382016

Medium

302F16

382F16

303016

303F16

383016

383F16

0316

310016

390016

1016

Large

310F16

390F16

311016

311F16

391016

391F16

1116

Horizontal display start position

34F016

3CF016

4F16

34FF16

3CFF16

Fig. 26 Display start position of each character size

(horizontal direction)

350016

350F16

3D0016

3D0F16

5016

35D016

3DD016

5D16

35DF16

3DDF16

35E016

35EF16

3DE016

3DEF16

5E16

5F16

35E016

3DF016

35FF16

3DFF16

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

The character code used to specify a character to be displayed is

determined based on the address in the CRT display ROM in which

that character is stored.

In other words, character code for any given character is configured

with two middle digits of the four-digit (hexnotated) addresses 300016

to 35FF16 where data for that character is stored.

Assume that data for one character is stored at addresses 3XX016 to

3XXF16 (XX denotes 0016 to 5F16) and addresses 3YY016 to 3YYF16

(YY denotes 8016 to DF16), then the character code for it is “XX16”.

Table 6 lists the character codes.

bit 7

bit 0

bit 7

bit 3

bit 0

3XX016

3XX016 80016

3XXF16 80016

3XXF16

Fig. 27 Display character stored area

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

➁ RAM for display (address 200016 to 20B116)

The CRT display RAM is allocated at addresses 200016 to 20B116,

and is divided into a display character code specifying part and dis-

play color specifying part for each block.

Table 7 shows the contents of the CRT display RAM.

When a character is to be displayed at the first character (leftmost)

position in block 1, for example, it is necessary to write the character

code to the seven low-order bits (bits 0 to 6) in address 200016 and

the color register No. to the two low-order bits (bits 0 and 1) in ad-

dress 208016. The color register No. to be written here is one of the

four color registers in which the color to be displayed is set in ad-

vance. For details on color registers, refer to (5) Color Registers.

The structure of the CRT display RAM is shown in Figure 27.

Table 7. The contents of the CRT display RAM

Block

Display position (from left)

1st character

Character code specification

Color specification

208016

200016

200116

2nd character

208116

3rd character

200216

208216

Block 1

16th character

200F16

208F16

17th character

18th character

201016

201116

209016

209116

201216

209216

Not used

201F16

209F16

1st character

2nd character

202016

202116

20A016

20A116

3rd character

202216

20A216

Block 2

16th character

202F16

20AF16

17th character

18th character

203016

203116

20B016

20B116

203216

20B216

Not used

203F16

20BF16

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

Block 1

[Character specification]

1st character : 200016

18th character : 201116

Character code (0016 to 5F16)

Specify 96 characters

[Color specification]

1st character : 208016

18th character : 209116

Specify color select mode

00 : Color register 0 specification

01 : Color register 1 specification

10 : Color register 2 specification

11 : Color register 3 specification

Block 2

[Character specification]

1st character : 202016

18th character : 203116

Character code (0016 to 5F16)

Specify 96 characters

[Color specification]

1st character : 20A016

18th character : 20B116

Color register specification

00 : Color register 0 specification

01 : Color register 1 specification

10 : Color register 2 specification

11 : Color register 3 specification

Fig. 28 Structure of the CRT display RAM

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

(5) Color Registers

(6) Multiline Display

The color of a displayed character can be specified by setting the

color to one of the four color registers (CO0 to CO3 : addresses

00E616 to 00E916) and then specifying that color register with the

CRT display RAM.

The M37210M3-XXXSP can normally display two lines on the CRT

screen by displaying two blocks at different vertical positions.

In addition, it allows up to 16 lines to be displayed by using a CRT

interrupt.

There are three color outputs : R, G and B. By using a combination

The CRT interrupt works in such a way that when display of one

block is terminated, an interrupt request is generated.

In other words, character display for a certain block is initiated when

the scanning line reaches the display position for that block (speci-

fied with vertical position register) and when the range of that block

is exceeded, an interrupt is applied.

of these outputs, it is possible to set 2 -1 (when no output) = 7 col-

ors. However, because only four color registers are available, up to

four colors can be displayed at one time.

R, G and B outputs are set by using bits 1 to 3 in the color register.

Bit 5 is used to specify whether a character output or blank output.

Figure 29 shows the structure of the color register.

Note : A CRT interrupt does occurs at the end of display regardless

of display on or off. In other words, even if a block is set to off

display with the display control bit of the CRT control register

(address 00EA16), a CRT interrupt request occurs (refer to

Figure 30).

Color registers 0,1,2,3

(CO0 : address 00E616)

(CO1 : address 00E716)

(CO2 : address 00E816)

(CO3 : address 00E916)

B signal output selection bit

0 : No character is output

1 : Character is output

G signal output selection bit

0 : No character is output

1 : Character is output

R signal output selection bit

0 : No character is output

1 : Character is output

OUT signal output selection bit (Note)

0 : OUT pin outputs character

1 : OUT pin outputs blank

Note : When the character bordering function is used, the contents

of this bit (bit 5) are invalied, and the OUT pin output be-

comes a border output.

Fig. 29 Structure of color registers

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

Block 1 (on display)

“CRT interrupt”

Block 2 (on display)

“CRT interrupt”

Block 1’ (on display)

“CRT interrupt”

Block 2’ (on display)

“CRT interrupt”

On display (“CRT interrupt” works after block)

Block 1 (off display)

“CRT interrupt”

Block 2 (off display)

“CRT interrupt”

Block 1’ (off display)

“CRT interrupt”

Block 2’ (off display)

“CRT interrupt”

Off display (“CRT interrupt” occurs after block)

(Note) : That is to say, “CRT interrupt” occurs even when it is off display by setting the display control flag of the CRT control

Fig. 30 Timing of CRT interrupt

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

(7) Character Border Function

Border can be specified in units of block by using the border select

the values set in the border select register and the character border

function. Figure 32 shows the structure of the border select register.

An border of a one clock (one dot) equivalent size can be added to a

character to be displayed in both horizontal and vertical directions.

The border is output from the OUT pin. In this case, bit 5 in the color

der is output from the OUT pin instead.

Table 8. The relationship between the value set in the border selection register and the character border function

Border selection register

Functions

Example of output

MDn0

R, G, B output

OUT output

Ordinary

R, G, B output

OUT output

Border including character

Border selection register

(MD : address 00E516)

Block 1 OUT signal output border selection bit

0 : Same output as R, G, B is output

1 : Border output

Block 2 OUT signal output border selection bit

0 : Same output as R, G, B is output

1 : Border output

Fig. 32 Structure of border selection register

is border.

is display by character data.

Fig. 31 Example of border

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

(8) CRT Output Pin Control

CRT output pins R, G, B and OUT are respectively shared with port

P52, P53, P54 and P55. When the corresponding bits in the port P5

control register (address 00CB16) are cleared to “0”, the pins are set

for CRT output ; when the bits are set to “1”, the pins function as port

P5 (general- purpose output pins).

The polarities of CRT outputs (R, G, B and OUT, as well as HSYNC

and VSYNC) can be specified by using the CRT port control register

(address 00EC16).

Use bits 0 to 4 in the CRT port control register to set the output po-

larities of HSYNC, VSYNC, R/G/B and OUT. When these bits are

cleared to “0”, a positive polarity is selected ; when the bits are set to

“1”, a negative polarity is selected.

Bits 5 to 7 in the CRT port control register are used to specify pin by

pin whether normal video signals or R-MUTE, G-MUTE, and B-

MUTE signals are output from each pin (R, G, B). When set for R-

MUTE, G-MUTE, and B-MUTE outputs, the whole background

colors of the screen become red, green, and blue.

Figure 33 shows the structure of the CRT port control register.

Polarity register

(CRTP : address 00EC16)

HSYNC input polarity selection bit

0 : Positive polarity

1 : Negative polarity

VSYNC input polarity selection bit

0 : Positive polarity

1 : Negative polarity

R/G/B output polarity selection bit

0 : Positive polarity

1 : Negative polarity

OUT output polarity selection bit

0 : Positive polarity

1 : Negative polarity

R pin output switch bit

0 : R signal output

1 : R-MUTE signal output

G pin output switch bit

0 : G signal output

1 : G-MUTE signal output

B pin output switch bit

0 : B signal output

1 : B-MUTE signal output

Fig. 33 Structure of CRT port control register

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

larity (falling transition).

INTERRUPT INTERVAL DETERMINATION

FUNCTION

3. The reference clock is selected by using bit 1 of the interrupt inter-

val determination control register. When the bit is cleared to “0”, a

64ms clock is selected ; when the bit is set to “1”, a 32µs clock is

selected (based on an oscillation frequency of 4MHz in either

case).

The M37210M3-XXXSP incorporates an interrupt interval determina-

tion circuit. This interrupt interval determination circuit has an 8-bit

binary up counter as shown in Figure 34.

Using this counter, it determines an interval or a pulse width on the

INT1 or INT2 (refer to Figure 36).

4. Simultaneously when the input pulse of the specified polarity (ris-

ing or falling transition) occurs on the INT1 pin (or INT2 pin), the 8-

bit binary up counter starts counting up with the selected

reference clock (64µs or 32µs).

The following describes how the interrupt interval is determined.

1. The interrupt input to be determined (INT1 input or INT2 input) is

selected by using bit 2 in the interrupt interval determination con-

trol register (address 00D816). When this bit is cleared to “0”, the

INT1 input is selected ; when the bit is set to “1”, the INT2 input is

selected.

5. Simultaneously with the next input pulse, the value of the 8-bit bi-

nary up counter is loaded into the determination register (address

00D716) and the counter is immediately reset (0016). The refer-

ence clock is input in succession even after the counter is reset,

and the counter restarts counting up from “0016”.

2. When the INT1 input is to be determined, the polarity is selected

by using bit 3 of the interrupt interval determination control regis-

ter ; when the INT2 input is to be determined, the polarity is se-

lected by using bit 4 of the interrupt interval determination control

6. When count value “FE16” is reached, the 8-bit binary up counter

stops counting. Then, simultaneously when the next reference

clock is input, the counter sets value “FF16” to the determination

When the relevant bit is cleared to “0”, determination is made of

the interval of a positive polarity (rising transition) ; when the bit is

set to “1”, determination is made of the interval of a negative po-

32µs

Control

circuit

8-bit binary up counter

64µs

RE0

RE1

INT2

Interrupt interval determination register

INT1

(Note)

RE2

Address 00D716

Selection gate : Connected to black

colored side at reset.

Data bus

RE : Interrupt interval determination control register

Note : The pulse width of external interrupt INT1 and INT2 needs 5 or more machine cycles.

Fig. 34 Block diagram of interrupt interval determination circuit

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

Interrupt interval determination control register

(RE : address 00D816

)

Interrupt interval determination circuit operation control bit

0 : Stop

1 : Operation

Reference clock selection bit (At f (XIN) = 4MHZ)

0 : 64ms

1 : 32ms

External interrupt input pin selection bit

0 : INT1 input

1 : INT2 input

INT1 pin input polarity switch bit

0 : Positive polarity input

1 : Negative polarity input

INT2 pin input polarity switch bit

0 : Positive polarity input

1 : Negative polarity input

Interrupt interval determination mode switch bit

0 : Interrupt interval determination mode

1 : Pulse width determination mode

Fig. 35 Structure of interrupt space distinguish control register

INT1 or 2 input

RE5

RE4 (RE3)

count interval

REi : Bitsi (i = 3, 4, 5) of interrupt space distinguish control register (address 00D816)

Fig. 36 Interrupt space distinguish control register setting value and the measuring interval

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

XIN

RESET

Internal RESET

SYNC

Address

Data

AD^H,

00,S 00,S-1 00,S-2 FFFE FFFF

Reset address from the vector table

PCH

PCL

ADL

ADH

Note 1 : f (XIN) and f (φ) are in the relationship : f (XIN) = 2 · f (φ).

2 : A question mark (?) indicates an undefined state that

depends on the previous state.

32768 count of XIN clock cycle (Note 3)

3 : Immediately after a reset, FF16 is automatically set in

timer 3 and 0716 in timer 4 and timer 4, timer 3 and the

clock (f (XIN) divided by 16) are connected in series.

Reset state is canceled by the overflow signal of timer 4.

Fig. 39 Reset sequence

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

I/O PORTS

(1) Port P0

(4) Port P3

Port P3 are a 2-bit I/O port and a 4-bit input port with function

Port P0 is an 8-bit I/O port with N-channel open-drain output.

similar to port P2, but the output structure of P30, P31 is CMOS

As shown in the memory map (Figure 3), port P0 can be ac-

cessed at zero page memory address 00C016.

output.

P32, P33 are in common with the external clock input pins of timer

Port P0 has a directional register (address 00C116) which can be

used to program each individual bit as input (“0”) or as output

(“1”). If the pins are programmed as output, the output data is

latched to the port register and then output. When data is read

from the output port the output pin level is not read, only the

latched data in the port register is read. This allows a previously

output value to be read correctly even though the output voltage

level is shifted up or down.

2 and 3.

P34, P35 are in common with the external interrupt input pins

INT1, INT2 and P35 with the analog input pin of A-D comparator

A-D4.

(5) Port P4

Port P4 are a 2-bit I/O port and a 1-bit input port with function

similar to port P2, but the output structure is N-channel open-

drain output.

Pins set as input are in the floating state and the signal levels can

thus be read. When data is written into the input port, the data is

latched only to the port latch and the pin still remains in the float-

ing state.

When a serial I/O function is selected, P40-P42 are in common

with pins SOUT, SCLK and SIN.

(6) OSC1, OSC2 pins

Clock input/output pins for CRT display function.

(7) HSYNC, VSYNC pins

Ports P00-P03 are in common with 6-bit PWM outputs PWM4-

PWM7. For the M37211M2, ports P00 and P01 are in common

with 6-bit PWM outputs PWM4 and PWM5.

HSYNC is a horizontal synchronizing signal input pin for CRT dis-

play.

(2) Port P1

VSYNC is a vertical synchronizing signal input pin for CRT display.

(8) R, G, B, OUT pins

Port P1 has basically the same function as port P0 except the

output structure is CMOS output. But, pins P15-P17 are input

ports and in common with analog input pins A-D1-A-D3.

This is an 4-bit output pin for CRT display and in common with

P52-P55.

(3) Port P2

Port P2 has basically the same function as port P1.

(9) Port P6

Port P6 is an 4-bit output port with function similar to port P0, but

the output structure is N-channel opendrain output.

This port is in common with 6-bit PWM output pin PWM0-PWM3.

(10) D-A pin

This is a 14-bit PWM output pin.

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

N-channel open-drain output

Port P0

Directional register

Port latch

Data bus

Port P10 – P14, P2, P30, P31

CMOS 3-state output

Directional register

Port latch

Port P10 – P14, P2, P30, P31

Data bus

Port P40,P41

Data bus

N-channel open-drain output

Port P40,P41

Directional register

Port latch

SIN/SCLK

Note : P40, P41 can also be used as

serial I/O pins.

Fig. 40 I/O pin block diagram (1)

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

N-channel open-drain output

Port P6

Data bus

Port latch

Note : P6 can also be used as

6-bit PWM output pins.

D-A, R, G, B, OUT

CMOS output

HSYNC, VSYNC

Internal circuit

Schmitt input

Internal circuit

HSYNC, VSYNC

D-A, R, G, B, OUT

Note : Pins R, G, B, and OUT can also be

used as output ports P52 – P55.

Port P15 – P17

Data bus

TIM2, TIM3,

INT1, INT2,

or SIN

Ports P32 – P35, P42

Port P15 – P17

Data bus

Note : P15 – P17 are in common with input Pins for A-D comparator.

P32, P33 are in common with timer inputs.

P34, P35 are in common with external interrupt inputs.

P42 is in common with input pins of serial I/O pins.

Fig. 41 I/O pin block diagram (2)

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

CLOCK GENERATING CIRCUIT

The example of external clock usage is shown in Figure 43 XIN is the

input, and XOUT is open.

The built-in clock generating circuit is shown in Figure 44.

When the STP instruction is executed, the internal clock φ stops os-

cillating at “H” level. At the same time, timers 3 and 4 are connected

in hardware and “FF16” is set in the timer 3, “0716” is set in the timer

4. Select f(XIN)/16 as the timer 3 count source (set bit 0 of the timer

34 mode register to “0” before the execution of the STP instruction).

And besides, set the timer 3 and timer 4 interrupt enable bits to dis-

abled (“0”) before execution of the STP instruction.

M37210M3-XXXSP

XIN

XOUT

The oscillator is restarted when an external interrupt is accepted.

However, the internal clock φ keeps its “H” level until timer 4 over-

flows.

CIN

COUT

This is because the oscillator needs a set-up period if a ceramic reso-

nator or a quartz-crystal oscillator is used.

When the WIT instruction is executed, the internal clock φ stops in the

“H” level but the oscillator continues running. This wait state is

cleared when an interrupt is accepted (Note). Since the oscillation

does not stop, the next instructions are executed at once.

To return from the stop or the wait state, set the interrupt enable bit to

“1” before executing the STP or the WIT instruction.

Note : In the wait mode, the following interrupts are invalid.

(1) VSYNC interrupt

Fig. 42 Ceramic resonator circuit example

M37210M3-XXXSP

XIN

(2) CRT interrupt

(3) Timer 2 interrupt using P32/TIM2 pin input as count source

(4) Timer 3 interrupt using P33/TIM3 pin input as count source

(5) Timer 4 interrupt using f(XIN)/2 as count source

Vcc

External oscillation

The circuit example using a ceramic resonator (or a quartz crystal

oscillator) is shown in Figure 42.

circuit

Vss

Use the circuit constants in accordance with the resonator

manufacture’s recommended values.

Fig. 43 External clock input circuit example

Interrupt request

Interrupt

Reset

disable flag I

Reset

WIT

STP instruction

Internal clock φ

Timer 4

instruction

STP instruction

T34M0

TIM3

1/2

1/8

Timer 3

T34M2

Selection gate: Connected to black

colored side at reset.

XIN

XOUT

Fig. 44 Clock generating circuit block diagram

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

ABSOLUTE MAXIMUM RATINGS

Symbol

VCC

Parameter

Conditions

Ratings

– 0.3 to 6

Unit

Power source voltage

Input voltage CNVSS

All voltages are based on

VSS.

Output transistors are

cut off.

Input voltage P00 – P07, P10 – P17, P20 – P27,

P30 – P35, P40 – P42, HSYNC,

– 0.3 to VCC + 0.3

VSYNC, RESET, OSC1, XIN

Output voltage P10 – P14, P20 – P27, P30, P31,

P40, P41, R, G, B, OUT, D-A,

XOUT, OSC2

IOH

– 0.3 to VCC + 0.3

– 0.3 to 13

Output voltage P60 – P63, P00 – P07

“H” average output current R, G, B, OUT, P10 – P14,

P20 – P23, P30, P31,

D-A

0 to 1 (Note 1)

“L” average output current R, G, B, OUT, P10 – P14,

IOL1

P20 – P23, P30, P31, P40, P41

D-A

0 to 2 (Note 2)

IOL2

IOL3

“L” average output current P60 – P63, P00 – P07

“L” average output current P24 – P27

Power dissipation

0 to 1 (Note 2)

0 to 10 (Note 3)

550

°C

Ta = 25°C

Topr

Tstg

Operating temperature

– 10 to 70

Storage temperature

– 40 to 125

°C

(VCC = 5V ± 10%, Ta = –10 to 70°C unless otherwise noted)

RECOMMENDED OPERATING CONDITIONS

Limits

Unit

Symbol

Parameter

Min.

4.5

Typ.

5.0

Max.

5.5

VCC

VSS

Power source voltage (Note 4)

Power source voltage

During the CPU and the CRT operation

“H” input voltage P00 – P07, P10 – P17, P20 – P27,

P30 – P35, P40 – P42, HSYNC,

VIH

0.8VCC

VCC

VSYNC, RESET, XIN, OSC1,

TIM2, TIM3, INT1, INT2, SIN, SCLK

“L” input voltage P00 – P07, P10 – P17, P20 – P27,

P30 – P35, P40 – P42

VIL

IOH

IOL1

0.4VCC

“L” input voltage TIM2, TIM3, INT1, INT2, SIN, SCLK,

HSYNC, VSYNC, RESET, XIN, OSC1

0.2VCC

“H” average output current (Note 1) R, G, B, OUT,

P10 – P14, P20 – P27, P30, P31, D-A

“L” average output current (Note 2) R, G, B, OUT, P10 – P14,

P20 – P23, P30, P31, P40, P41, D-A

IOL2

IOL3

fCPU

fCRT

fhs

“L” average output current (Note 2) P60 – P63, P00 – P07

“L” average output current (Note 3) P24 – P27

Oscillation frequency (for CPU operation)(Note 5)

Oscillation frequency (for CRT display)

Input frequency TIM2, TIM3, INT1, INT2

Input frequency SCLK

3.6

4.0

5.0

8.1

6.0

100

MHz

kHz

MHz

fhs

Notes1: The total current that flows out of the IC should be 20mA (max.).

2: The total of IOL1 and IOL2 should be 30mA (max.).

3 : The total of IOL of port P24-P27 should be 20mA (max.).

4: Connect 0.022µF or more capacitor externally between the VCC – VSS power source pins so as to reduce power

source noise.

Also connect 0.068µF or more capacitor externally between the VCC – CNVSS pins.

5 : Use a quartz-crystal oscillator or a ceramic resonator for CPU oscillation circuit.

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

(VCC = 5V ± 10%, VSS = 0V, Ta = – 10 to 70°C, f (XIN) = 4MHz unless otherwise noted)

ELECTRIC CHARACTERISTICS

Limits

Typ.

Symbol

Parameter

Test conditions

Unit

Min.

–

Max.

OFF

VCC = 5.5V

f (XIN) = 4MHz

–

ICC

Power source current

OFF

–

VCC = 5.5V

f (XIN) = 8MHz

–

At stop mode

–

300

µA

“H” output voltage P10 – P14, P20 – P27,

P30, P31, R, G, B, OUT, D-A

VCC = 4.5V

IOH = – 0.5mA

VOH

VOL

2.4

“L” output voltage P10 – P14, P20 – P23, P30, P31, VCC = 4.5V

0.4

P40, P41, R, G, B, OUT, D-A

IOL = 0.5mA

“L” output voltage P60 – P63, P00 – P07

VCC = 4.5V

IOL = 0.5mA

“L” output voltage P24 – P27

Hysteresis RESET

VCC = 4.5V

IOL = 10.0mA

3.0

0.7

1.3

VCC = 5.0V

0.5

–

VT + VT–

Hysteresis (Note) HSYNC, VSYNC, TIM2, TIM3,

INT1, INT2, SIN, SCLK

VCC = 5.0V

“H” input leak current RESET, P00 – P07,

P10 – P17, P20 – P27,

VCC = 5.5V

VI = 5.5V

IIZH

µA

P30 – P35, P40 – P42, HSYNC, VSYNC

“L” input leak current RESET, P00 – P07,

P10 – P17, P20 – P27, P30 – P35,

VCC = 5.5V

VI = 0V

IIZL

µA

P40 – P42, P60 – P63, HSYNC, VSYNC

“H” input leak current

P60 – P63, P00 – P07

VCC = 5.5V

VO = 12V

IOZH

Note : P3₂– P3₅, have the hysteresis when these pins are used as interrupt input pins or timer input pins.

P4₀– P4₂have the hysteresis when these pins are used as serial I/O ports.

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

GZZ–SH06–09B < 25C0 >

Mask ROM number

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37210M3-XXXSP/FP

Date :

MITSUBISHI ELECTRIC

Section head Supervisor

signature

Note : Please fill in all items marked ❈.

Submitted by Supervisor

TEL

(

Company

name

)

❈

Customer

Date

issued

Date :

❈ 1. Confirmation

Specify the name of the product being ordered and the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on

this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce

differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

Microcomputer name :

M37210M3-XXXSP

M37210M3-XXXFP

(hexadecimal notation)

Checksum code for entire EPROM

EPROM type (indicate the type used)

27256

EPROM address

0000¹⁶

Product name

ASCII code :

‘M37210M3 –’

000F16

100016

Character ROM1

15FF16

180016

Character ROM2

1DFF16

500016

ROM (12K bytes)

7FFF16

(1)

(2)

Set “FF16” in the shaded area.

Write the ASCII codes that indicates the product name of “M37210M3–” to addresses 0000¹⁶to 000F16

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate

mark specification form (52P4B for M37210M3-XXXSP; 64P6N for M37210M3-XXXFP) and attach to the mask ROM

confirmation form.

❈ 3. Comments

(1/3)

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

GZZ–SH06–09B < 25C0>

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37210M3-XXXSP/FP

MITSUBISHI ELECTRIC

The structure of character ROM (divided of 12✕16 dots font)

Example

Character code

“1A¹⁶

”

Character

ROM2

Character

ROM1

b6 b5 b4 b3 b2 b1 b0

Example 11A0¹⁶

Example 19A0¹⁶

00¹⁶

F016

0416

F016

11AF¹⁶

19AF¹⁶

0A16

F016

1116

F016

1116

F016

F16

2016

F816

3F16

F816

4016

F416

4016

0016

F416

F016

0016

F016

(3/3)

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

GZZ–SH06–10B < 25B0 >

Mask ROM number

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37210M4-XXXSP

Date :

MITSUBISHI ELECTRIC

Section head Supervisor

signature

Note : Please fill in all items marked ❈.

Submitted by Supervisor

TEL

(

Company

name

)

❈

Customer

Date

issued

Date :

❈ 1. Confirmation

Specify the name of the product being ordered and the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on

this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce

differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

(hexadecimal notation)

Checksum code for entire EPROM

EPROM type (indicate the type used)

27256

EPROM address

0000¹⁶

Product name

ASCII code :

‘M37210M4 –’

000F16

100016

15FF16

Character ROM1

Character ROM2

180016

1DFF16

400016

ROM (16K bytes)

7FFF16

(1)

(2)

Set “FF16” in the shaded area.

Write the ASCII codes that indicates the product name of “M37210M4–” to addresses 0000¹⁶to 000F16

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate

mark specification form (52P4B for M37210M4-XXXSP) and attach to the mask ROM confirmation form.

❈ 3. Comments

(1/3)

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

GZZ–SH06–10B < 25B0 >

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37210M4-XXXSP

MITSUBISHI ELECTRIC

The structure of character ROM (divided of 12✕16 dots font)

Example

Character code

“1A¹⁶

”

Character

ROM2

Character

ROM1

b6 b5 b4 b3 b2 b1 b0

Example 11A0¹⁶

Example 19A0¹⁶

00¹⁶

F016

0416

F016

11AF¹⁶

19AF¹⁶

0A16

F016

1116

F016

1116

F016

F16

2016

F816

3F16

F816

4016

F416

4016

0016

F416

F016

0016

F016

(3/3)

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

GZZ–SH06–11B < 25B1 >

Mask ROM number

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37211M2-XXXSP

Date :

MITSUBISHI ELECTRIC

Section head Supervisor

signature

Note : Please fill in all items marked ❈.

Submitted by Supervisor

TEL

(

Company

name

)

❈

Customer

Date

issued

Date :

❈ 1. Confirmation

Specify the name of the product being ordered and the type of EPROMs submitted.

Three EPROMs are required for each pattern.

If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on

this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce

differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.

Checksum code for entire EPROM

EPROM type (indicate the type used)

(hexadecimal notation)

27256

EPROM address

0000¹⁶

Product name

ASCII code :

‘M37211M2 –’

000F16

100016

15FF16

Character ROM1

Character ROM2

180016

1DFF16

600016

ROM (8K bytes)

7FFF16

(1)

(2)

Set “FF16” in the shaded area.

Write the ASCII codes that indicates the product name of “M37211M2–” to addresses 0000¹⁶to 000F16

❈ 2. Mark specification

Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate

mark specification form (52P4B for M37211M2-XXXSP) and attach to the mask ROM confirmation form.

❈ 3. Note

(1)

Set the stack page selection bit to “0”, because this bit is set to “1” after reset but the internal RAM is located at 0

page only.

(2)

Both P02 pin (9th pin) and P03 pin (10th pin) are not used as PWM output pins.

❈ 4. Comments

(1/3)

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

GZZ–SH06–11B < 25B1 >

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37211M2-XXXSP

MITSUBISHI ELECTRIC

The structure of character ROM (divided of 12 ✕16 dots font)

Example

Character code

“1A¹⁶

”

Character

ROM1

Character

ROM2

6 b5 b4 b3 b2 b1 b0

Example

11A016

Example

19A016

00¹⁶

0416

0A16

1116

2016

3F16

4016

0016

F016

F816

F416

F016

11AF¹⁶

19AF¹⁶

(3/3)

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP

M37210E4-XXXSP/FP, M37210E4SP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

with ON-SCREEN DISPLAY CONTROLLER

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP,

REVISION DESCRIPTION LIST

M37210E4-XXXSP/FP, M37210E4SP/FP

DATA SHEET

Rev.

date

Revision Description

No.

1.0 First Edition

9708

2.0 Information about copyright note, revision number, release date added (last page).

971130

(1/1)

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