FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N-A)
Clock
input
X
IN
Reset input
RESET
V
SS
32
27
73
Clock
output
X
OUT
(5V)
V
CC
(0V)
30
28
31
29
1
Data bus
Clock generating
circuit
CPU
A
ROM
X
Y
S
PC
H
Timer X(16)
Timer Y(16)
Timer 1(8)
Timer 3(8)
Timer 2(8)
PS
PC
L
LCD display
RAM
(20 bytes)
LCD
drive control
circuit
RAM
8
7
6
5
4
3
2
1
80
79
78
77
76
75
74
72
71
70
69
68
67
66
65
V
L1
V
L2
V
L3
COM
0
COM
1
COM
2
COM
3
X
CIN
Sub-
clock
input
X
COUT
Sub-
clock
output
φ
Watchdog timer
RESET
SI/O2(8)
SI/O1(8)
T
OUT
CNTR
0
,CNTR
1
RTP
0
,RTP
1
SEG
0
SEG
1
SEG
2
SEG
3
SEG
4
SEG
5
SEG
6
SEG
7
SEG
8
SEG
9
SEG
10
SEG
11
SEG
12
SEG
13
SEG
14
SEG
15
X
CIN
INT
0
,INT
1
Real time port function
X
COUT
φ
INT
2
Key-on wake up
P7(2)
P5(8)
P3(8)
P4(8)
P6(2)
P2(8)
P1(8)
P0(8)
P0(8)
28 29
9 10
19 20 21 22 23 24 25 26
11 12 13 14 15 16 17 18
57 58 59 60 61 62 63 64
33 34 35 36 37 38 39 40
41 42 43 44 45 46 47 48
49 50 51 52 53 54 55 56
I/O port P7
I/O port P5
I/O port P4
I/O port P6
Input port P3
I/O port P2
I/O port P1
I/O port P0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3820 Group
3
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
