SL1461SA
ABSOLUTE MAXIMUM RATINGS
cont.
All voltages are referred to V
EE
at 0V
Characteristics
MP16 package thermal resistance,
chip to case
Power consumption at 5.5V
ESD protection - pins 1 to 15
ESD protection - Pin 16
2
1.7
Min.
Typ.
41
250
Max.
°C/W
mW
kV
kV
Mil-std-883 method 3015 class 1
Mil-std-883 method 3015 class 1
Conditions
2K
AGC BIAS
RV1
50K
AFC WINDOW ADJUST
RV2
C1
47nF
C2
100nF
R1
1
2
16
15
100nF
27K
R6
C3
47 F
C4
+5V
1nF
C12
D1
BB515
C5
4K7
TP4
R5
1K2
R4
100pF
C11
C10
TP2
VIDEO OUTPUT
TP1
SL1461SA
3
4
14
13
12
11
10
9
BB515 470nF
D2
TP3
4n7
C6
R2
5K1
4K7
R3
C7
1nF
5
6
7
8
100pF
1K2
C9
47 F
C8
1nF
RF INPUT
Fig.3 Standard application circuit
FUNCTIONAL DESCRIPTION
The SL1461SA is a wideband PLL FM demodulator,
optimised for application in satellite receiver systems and
requiring a minimum external component count. It contains all
the elements required for construction of a phase locked loop
circuit, with the exception of tuning components for the local
oscillator, and an AFC detector circuit for generation of error
signal to correct for any frequency drift in the outdoor unit local
oscillator. A block diagram is contained in Fig. 2 and the typical
application in Fig. 3.
The internal pin connections are contained in Fig.6/6a
In normal applications the second satellite IF frequency of
typically 402 or 479.5MHz is fed to the RF preamplifier, which
has a working sensitivity of typically -40 dBm, depending on
application and layout. The preamplifier contains an RF level
detect circuit, which generates an AGC signal that can be used
for controlling the gain of the IF amplifier stages, so maintaining
a fixed level to the RF input of the SL1461SA, for optimum
threshold performance. The bias point of the AGC circuit can
be adjusted to cater for variation in AGC line voltage
requirement and device input power. The typical AGC curves
are shown in Fig. 9. It is recommended that the device is
operated with an input signal between -30 and -35dBm. This
ensures optimum linearity and threshold performance, and
gives a good safety margin over the typical sensitivity of
-40dBm.
The output of the preamplifier is fed to the mixer section
which is of balanced design for low radiation. In this stage the
RF signal is mixed with the local oscillator frequency, which is
generatedby an on–board oscillator. The oscillator block uses
an external varactor tuned sustaining network and is optimised
for high linearity over the normal deviation range. A typical
frequency versus voltage characteristic for the oscillator is
contained in Fig. 7. The loop output is designed to compensate
for first order temperature variation effects; the typical stability
is shown in Fig. 8
The output of the mixer is then fed to the loop amplifier
around which feedback is applied to determine loop transfer
characteristic . Feedback can be applied either in differential or
single ended mode; if the appropriate phase detector gains are
assumed in calculating loop filters, both modes should give the
same loop response.
The loop amplifier drives a 75Ω output impedance buffer
amplifier, which can either be connected to a 75Ω load or used
to drive a high input impedance stage giving greater linearity
and approximately 6dB higher demodulated signal output
level.
4
MITEL [ MITEL NETWORKS CORPORATION ]
