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PDSP16515AB0AC 参数 Datasheet PDF下载

PDSP16515AB0AC图片预览
型号: PDSP16515AB0AC
PDF下载: 下载PDF文件 查看货源
内容描述: 单机FFT处理器 [Stand Alone FFT Processor]
分类和应用: 外围集成电路
文件页数/大小: 27 页 / 292 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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PDSP16515A
is defined below where Ø is in MHz and L is the system clock
low time in nanoseconds :
S = FØ,
where F =
4 / (6+0.001ØL)
purpose. The edge is provided by INEN going low. Loading
will cease when a complete block (or group of blocks with
multiple concurrent transforms) of data has been loaded, even
if INEN remains low. INEN must go high at some point after the
minimum hold time has been satisfied, and then return low
AFTER ALL DATA HAS BEEN LOADED, before a new load
operation can commence. Low going edges which occur
before all data has been loaded will be ignored.
F is typically 0.66 and applies to all transforms except for those
of 1024 points, even if INEN is driven such that concurrent
operations do not actually occur (Note also that S must be
synchronous to SCLK). If this causes a system limitation in a
single device application, then the device can be configured
for pseudo, Mode 2, multiple device operation. Separate load,
transform, and then dump operations will then always occur,
but DEN must be low when a transform is complete or DAV will
never go active. See the section on multiple device operation.
Loading Data
Data loading is controlled by three signals; DIS an input
strobe, INEN a load enable, and LFLG an output flag. Detailed
timing information is given in Table 1. Once sufficient data has
been acquired, a transform will automatically commence. This
is normally after a complete block has been loaded, except
when a single device is performing overlapped transforms of
256 points or less. With 75% overlapping, transforms will
commence after 25% of a new block has been loaded, and
with 50% overlapping transforms commence after 50% of the
data has been loaded. The remainder of the block is provided
by data already stored in the internal RAM.
The data strobe is used to load data into the internal
workspace RAM, and data must meet the specified set up and
hold times with respect to its rising edge. DIS can be a
continuous input since the device only loads data when an
input enabling signal is active.
An internal synchronisation interval is necessary between the
last sample being loaded with the DIS strobe and transforms
being started with the system clock. This can be up to twelve
system clock periods when data transfers and transforms are
overlapped. The transform times given later in Table 4 are
maximum values, and include these twelve periods.
The way in which the INEN signal controls data loading is
dependent on whether a single or multiple device is to be
implemented, and the status of Control Register Bit 12.
When Bit12 is set in a SINGLE device system the INEN signal
is simply used as an enable for the DIS strobes. When INEN
is low, and provided the relevant set up and hold times have
been satisfied, data will be loaded with the rising edge of the
DIS strobe. If no gaps occur within the incoming data, INEN
can be tied permanently low, provided that the sampling rate
has been chosen such that transforms are completed before
a new block of data is loaded. For transforms of less than 1024
points, data will then be continually processed without any
loss of information. In the 1024 point modes the device will
cease loading data when 1024 samples have been loaded,
and even if INEN remains low no more data will be accepted
until the previous results have been dumped.
In a multiple device system an edge is ALWAYS needed to
commence a load operation, and Bit 12 has a different
The INEN edge mode is actually provided for the correct
operation of multiple device systems, but if Bit 12 in the Control
Register is reset in the SINGLE device mode, the edge
activated operation will still be possible. With all but 256 point
complex transforms, the single device edge mode of
operation is identical to that of a multiple device system. With
256 point transforms, and their concurrent derivatives, the
location of the low going edge in the data stream is dependent
on the amount of block overlapping. The low going edge
transition must be provided after 64 samples have been
loaded with 75% overlapping, and after 128 samples have
been loaded with 50% overlapping. With no overlapping the
edge must be provided after 256 samples have been loaded.
In a single device system with Bit 12 set, INEN can be taken
high to inhibit the load operation when gaps occur in the data
stream. In the INEN edge activated mode gaps in the data
stream can only be accommodated if the DIS clock is
externally inhibited. Taking INEN high will not inhibit the
loading of data in this mode.
With gaps in the data stream the peak sampling rates can be
higher than continuous sampling rates. When data loading is
not coincident with transform operations the peak rate can
equal that of the system clock, otherwise it is reduced by the
factor, F, given on the opposite page.
When Control Register Bit 12 is set in any multiple device
mode, the DEF high going edge will also initiate a load
operation after it has been internally synchronised to the rising
DIS edge. If the first device in a multiple device system is
programmed in this manner, the transform sequence will
automatically start when DEF goes in-active. The other
devices need the INEN edge as usual, and must have Bit 12
reset. A fuller explanation of the use of Bit 12 in a multiple
device mode is given in the section on I/O In Multiple Device
Systems. Note that the use of Bit 12 in a single device system
( Control Register Bits 10:9 = 00) is completely different to its
use in a multiple device mode.
The LFLG output goes active in response to the DIS rising
edge used to load the first data sample, and indicates that a
load operation is occurring. In an edge activated system the
LFLG output will go high as the result of the first high going DIS
edge after INEN has gone low. In the simple INEN enabling
mode, internal logic counts the number of valid inputs and
detects when the programmed block length has been
reached. LFLG then goes low and will go high again in
response to the next valid DIS strobe. LFLG will go low when
DEF is active and will go high in response to the first INEN
enabled DIS edge after DEF has gone in- active.
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