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PDSP16510AA0GC 参数 Datasheet PDF下载

PDSP16510AA0GC图片预览
型号: PDSP16510AA0GC
PDF下载: 下载PDF文件 查看货源
内容描述: 单机FFT处理器 [Stand Alone FFT Processor]
分类和应用: 外围集成电路
文件页数/大小: 25 页 / 273 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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PDSP16510  
noted that the amount of overlap between I/O transfers and  
transforms is completely under the control of the system, since  
an input enable signal (INEN) and an output enable (DEN) can  
be used to initiate transfers.  
within 32 words.  
If no incoming data is to remain un-processed, the user  
must ensure that the time taken to acquire sufficient data to  
instigate a new transform is greater than or equal to the  
transformation time itself. The latter can be calculated from  
Table 4, once the system clock rate has been defined. When  
1024 point transforms are performed, both the time to read  
data from the input buffer, and also the time to dump data,  
must be included in the calculation to determine the minimum  
time in which data can be loaded into the external buffer.  
The peak transfer rate is limited by the characteristics of  
the I/O circuits, but can be greater than the sampling rate  
which is determined by the transform time. When load and  
dump operations are not concurrent with transform operations  
( as in the 1024 point modes ), then the maximum I/O rate is  
equal to the system clock rate, Ø. When other transform sizes  
are specified, the sampling rate, S, is reduced by a factor F.  
This is defined below where Ø is in MHz and L is the system  
clock low time in nanoseconds :  
In the 1024 point mode there is insufficient workspace for  
input and output buffering in addition to working memory. The  
device is then configured in a mode with separate load,  
transform and dump operations. The internal arrangement is  
shown in Fig. 5. The support of an external input buffer is  
needed if incoming samples are not to be lost whilst a  
transform is in progress. This is loaded at the sample clock  
rate and transferred to the FFT processor as quickly as  
possible. In this mode the PDSP16510 always expects to  
receive 1024 words, regardless of the amount of block over-  
lapping. Data stored internally cannot be re-used when block  
overlapping is required, and data from the external buffer must  
be re-read as necessary.  
Fig. 6 illustrates a typical 1024 point system with an input  
buffer which supports complex input data. The input buffer  
can be provided by a PDSP16540 Bucket Buffer without the  
need for any external control logic. It supplies RAM for 1024  
x 32 complex words, and allows transfers to the FFT Proces-  
sor at the full system clock rate. The PDSP16540 also sup-  
ports the standard 50% and 75% data block overlapping, but  
in addition allows the user to define the amount of overlap to  
S = FØ, where F = 4 / (6+0.001ØL)  
F is typically 0.66 and applies to all transforms except for those  
of 1024 points, even if INEN is driven such that concurrent  
operations do not actually occur (Note also that S must be  
1
N/2  
N
1
N
DIS  
DATA IN  
VALID  
TSD  
TSA  
THD  
THA  
TSI  
THI  
INEN  
LFLG  
50% Overlap  
TFH  
Min Time =THA  
TFL  
TFL  
TFH  
INEN  
Edge activated  
system  
TSA  
TED  
16510A,A0,B0,C0  
Characteristic  
Symbol  
Min  
Max  
Units  
Data In set up Time  
Data In Hold Time  
TSD  
THD  
TSA  
THA  
THI  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
INEN active going set up  
8
INEN active Hold Time  
0
INEN in-active Hold Time to ensure no load  
2
INEN in-active going set up for no load operation  
Delay to LFLG going active ( 30 pf load )  
Delay to LFLG going in-active ( 30 pf load )  
Min time to INEN low in edge mode  
TSI  
8
TFH  
TFL  
TED  
10  
10  
15  
Table 1. Advanced Timing Information with Continuous Inputs.  
6