PDSP16510
given previously.
This is loaded at the sampling rate and then data is transferred
to the PDSP16510 at a user defined rate. The time taken to
load this external buffer must be at least equal to the sum of
the time to transfer data in and out of the FFT processor and
the transform time itself. When data blocks are overlapped by
50% or 75%, no more than one half or one quarter of the block,
respectively, must have been loaded in the same time. In the
1024 point modes the dump time can be any user defined
value, and need not be increased to allow for block overlap-
ping. The dump time, however , does directly effect the
maximum sampling rates which can be accommodated with-
out loss of incoming data.
The time taken to dump the transformed data must be no
more than the load time, if continuous inputs are to be
supported and I/O operations are concurrent with transforms.
With block overlapping the dump time must be reduced to the
time taken to load the partial block. This dump time must
include four extra DOS strobes needed to prime the output
circuitry when a transform is complete. These, in effect, can be
added to the transform time such that with concurrent I/O and
0%, 50%, or 75% overlapping;
nS or (nS)/2 or (nS)/4 must be gtr than or equal to PK + 4W
The maximum sampling rates for 1024 point transforms
at any load and dump rate can be calculated from the following
relationship:
where n is the transform size, S is the input DIS period, P is
the number of clock periods given in Table 4, K is the system
clock period, and W is the DOS period which can be less than
S if necessary. Note also that S must be synchronous to
SCLK, and if an asynchronous ratio is required then a
pdsp16540 input buffer should be used.
When DIS and DOS are produced from a common source
the minimum allowable sampling period must be increased to
allow for the extra dumping time. Thus when DIS and DOS
have equal periods and, for example, there is no overlapping;
1024S or 512S or 256S > 1024B + PK + D
for 0%, 50%, or 75% overlapping respectively. S, P, and K
were defined opposite. B is the clock period in which data is
read from the input buffer and loaded into the device, D is the
total dump time allowing for the four extra DOS periods. The
periods of the load and dump clocks cannot be less than the
system clock period. The maximum sampling rates given in
Table 5 assume that a 40 MHz I/O rate is used, and that all
results are dumped.
(n - 4)S must be greater than or equal to PK
The maximum sampling rates given in Table 5 allow for the
extra dumping time.
MULTIPLE DEVICE SYSTEMS
The load and dump operations are not concurrent with
transforms in the 1024 point modes, and an external input
buffer will be needed if loss of incoming data is to be avoided.
In real time applications several devices may be used in
parallel in order to increase the sampling rate, but not to
increase the transform size. When all outputs are commoned
together, and feed a single output processor, then the data
dump time must always be less than or equal to the time taken
to load the data block ( or 50% or 25% of the time with block
overlapping ). In most configurations with block overlapping
the dump rate requirements will limit the maximum input rate,
if only one output processor is provided. This can be avoided
if the system provides separate output processors for every
device. The system clock used for internal calculations then
ultimately imposes a limit on the maximum sampling rate
possible.
A multiple device system performing complex transforms
with a single output processor is shown in Figure 9. The INEN/
LFLG signals are used to co-ordinate the segmentation of
data between devices. The in-active going edge of LFLG
instigates the load procedure in the next device, and, since
this edge can be programmed to occur either 25%, 50%, or
100% through the load operation, it can cause the next device
to commence loading before the previous one has finished. In
this manner data block overlapping is achieved. When mul-
tiple concurrent transforms are performed ( for example 4 x 64
or 8 x 64 ) two LFLG transitions are sometimes needed to
support block overlapping. This is fully explained in the section
on Mode 1 sampling rates.
Configuration
Parameters
Power on
Reset
Output
Clock
Complex Data
Input
IMAG
REAL
O/P
S
MAG'
PDSP16330
PDSP16510
PDSP16510
PDSP16510
PHASE
CLK
SCALE
TAG
IMAG
REAL
O/P
S
DATA
AVAIL'
IMAG
REAL
O/P
S
In any of the multiple device modes an INEN edge
transition is needed to start a new load procedure when the
previous one has finished. When the LFLG output from the last
device is fed back to the INEN input of the first device,
continuous transforms will be executed. This continuous
sequence can be started by the rising edge of DEF if Control
Register Bit 12 is set in the first device (see section on Loading
INPUT CLOCK
Fig 9. Multiple Device Configuration
12
MITEL [ MITEL NETWORKS CORPORATION ]
