欢迎访问ic37.com |
会员登录 免费注册
发布采购

PDSP16510AA0AC 参数 Datasheet PDF下载

PDSP16510AA0AC图片预览
型号: PDSP16510AA0AC
PDF下载: 下载PDF文件 查看货源
内容描述: 单机FFT处理器 [Stand Alone FFT Processor]
分类和应用: 外围集成电路
文件页数/大小: 25 页 / 273 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
 浏览型号PDSP16510AA0AC的Datasheet PDF文件第1页浏览型号PDSP16510AA0AC的Datasheet PDF文件第2页浏览型号PDSP16510AA0AC的Datasheet PDF文件第4页浏览型号PDSP16510AA0AC的Datasheet PDF文件第5页浏览型号PDSP16510AA0AC的Datasheet PDF文件第6页浏览型号PDSP16510AA0AC的Datasheet PDF文件第7页浏览型号PDSP16510AA0AC的Datasheet PDF文件第8页浏览型号PDSP16510AA0AC的Datasheet PDF文件第9页  
PDSP16510
SIGNAL
D15:0
AUX15:0
TYPE
I
I
DESCRIPTION
Data input during real only mode. The real component in complex data mode.
When DEF is active AUX15:0 are used to define the operating mode as defined in Table 3.
When DEF is in-active AUX15:0 either provide the 16 bit imaginary component of complex
input data, or a second set of real only inputs.
These pins output the real component of the transformed data when DAV and DEN are active.
Otherwise they are high impedance.
These pins output the imaginary component of the transformed data when DAV and DEN are
active. Otherwise they are high impedance.
The high going edge of DEF is used to internally latch the contents of AUX15:0, which then
define the operating mode. In the simplest system DEF is a power on reset. When DEF is low
the internal control logic is reset.
System clock used for internal computations.
These pins indicate the number of shifts towards the binary point which have occurred as the
result of the conditional scaling logic. When the data path right shift is restricted to 2 places
per pass, state 15 is used to indicate an overflow and only a total of 14 shifts is possible.
This flag indicates that data is being loaded into the device. It goes active in response to an
INEN input, and may be programmed to go in-active after the complete, one quarter, or one
half a data block has been loaded.
The use of this input is mode dependent. It is either used as an active low, load enabling,
signal for the DIS strobe, or it is used to initiate a new block load operation.
The rising edge of this input is used to load data into the device.
The rising edge of this input is used to dump data from the device. In most applications it may
be tied to the DIS input, even if the output rate must be higher than the input rate because of
overlapped data blocks. The DIS input is then internally divided down.
An active low signal that indicates that a transform is complete. Transformed data will then
be output in normal sequential order using DOS. It may be optionally programmed to be
delayed by 24 DOS strobes to match the delay through a PDSP16330.
This input is used to enable the data dump operation when DAV has gone active. If it is tied
low the device will automatically dump data when DAV goes active. Otherwise the device will
wait for the enabling signal to go low before the dump operation commences.
Only available in the 132 pin GC package. When high the block floating logic is disabled.
+5V pins
Ground pins
R15:0
O
I15:0
O
DEF
I
SCLK
S3:0
I
O
LFLG
O
INEN
I
DIS
DOS
I
I
DAV
O
DEN
I
DISAB
VDD
GND
I
P
P
NOTE.
All references to DEF, INEN, DAV, and DEN within the text do not contain the bar designator, signifying an active low
signal. This is considered to be implied by the signal name and is not meant to imply a change in the signal function.
FUNCTIONAL OPERATION
The PDSP16510 performs decimation in time, radix 4,
forward or inverse Fast Fourier Transforms. Data is loaded
into an internal workspace RAM in normal sequential order,
processed, and then dumped in the correct order. With real
only input data the processing time can approximately be
halved for a given transform size. Two real inputs then replace a
single complex input, and are processed in parallel.
Either a Blackman-Harris or a Hamming window can be
generated internally, and applied to the incoming real or complex
data with no time penalty. No external ROM is needed to support
these windows. The Blackman-Harris window gives improved
dynamic range over the Hamming window when two closely
3