PDSP16488A MA
LOADING REGISTERS FROM A HOST CPU
PC0
The expansion data inputs [X14:0] on a single or
master device are connected to the host bus to provide
address and data for the internal registers. In a multiple device
system the remaining devices receive addresses and data
which have been passed through the expansion connection
between earlier devices in the cascade chain. Each device
needs an individual chip enable plus a global data strobe,
read/write line, and
PROG
signal from the host.
Registers are individually addressed and can be
loaded in any sequence once the global
PROG
signal has
been produced by the host. The latter would normally be
produced from an address decode encompassing all the
necessary device addresses.
If a self timed system is to be implemented, a timing
strobe must be passed down the expansion chain through the
PC1/PC0
connections. The
PC0
output from the final device
is used as a host REPLY signal, and indicates that the last
device has received data after the propogation delay of
previous devices. The timing strobe is produced in the
MASTER device from the host data strobe, and will appear on
the
PC0
output. This feature allows the user to cascade any
number of devices without knowing the propogation delay
through each device. The timing information for this mode of
operation is given in Figure 8.
The host can also read the data contained in the
internal registers. The required device is selected using chip
enable with the R/W line indicating a read operation. Single
device systems output the data read on X7:0, but in multiple
device systems data is read from the D7:0 outputs on the final
device in the chain. These must be connected back to the host
data bus through three-state drivers. When earlier devices in
the chain are addressed, the register contents are transferred
through the expansion connections down to the final device.
In the self timed configuration the data will be valid when the
REPLY
goes active, as shown in Figure 8.
If the
REPLY
signal is not to be used , the
PC0/PC1
connections are not necessary, and the host data strobe for a
write operation must be wide enough to allow for the worst
case propogation delay through all the devices ( TDEL ). If the
data or address from the host does not meet the set up time
given in Fugure 8, the width of the data strobe can be simply
extended to compensate for the additional delay. When read-
ing data the access time required is: TACC + ( N - 1 ).TDEL
using the maximum times obtained from Figure 8.
An input from the previous PC1 output in a multiple
device chain. Not needed on a SINGLE device or
if the self timed feature is not used.
Reply to the host from a SINGLE device or from the
last device in a cascade chain. It indicates that the
write strobe can be terminated. Connected to PC0
input of the next device at intermediate points in the
chain if the self timed feature is used.
Read/Not Write line from the host CPU which is
connected to all devices in the system.
An active low enable which is normally produced
from a global address decode for the particular
device. This must encompass all internal register
addresses.
An active low host data strobe which is connected
to all devices. in the system.
An active low global signal, produced by the host,
which is connected to all devices in the system.
Together with a unique chip enable for every de-
vice, it allows the internal registers to be updated
or examined by the host. PROG and CE should be
tied together in a single device system.
PC1
R/W
CE
DS
PROG
LOADING REGISTERS FROM AN EPROM
In the EPROM supported mode, one device has to
assume the role of a host computer. If more than one device
is present, this must be the first component in the chain,
which must have its
MASTER
pin tied low.
The MASTER device contains internal address count-
ers which allow the registers in up to 16 cascaded devices to
be specified. It also generates the
PROG
signal and a data
strobe on the pins which were previously inputs. These
outputs must be connected to the other devices in the system,
which still use them as inputs. The R/W input should be tied
low on all devices.
The width of the data strobe is determined by the
feedback connection from the PC1 output on the last device
to the
PC0
input on the MASTER. The
PC0/PC1
connections
must be made between devices in a multiple device system;
in a single device system the connection is made internally.
The available EPROM access time is determined by
an internal oscillator and does not require the pixel clock to be
present during the programming sequence. Any pixel clock re-
synchronization in a real time system will thus not effect the
coefficient load operation. The relevent EPROM timing infor-
mation is shown in figure 9.
The load procedure will commence after reset has
gone from active to in-active, and will be indicated by the
PROG
output going active. The data from 73 EPROM loca-
tions will be loaded into the internal registers using addresses
corresponding to those in Table 3. Within a particular page of
128 EPROM locations, the first nine locations supply control
register information, and the top 64 supply coefficients. The
middle 55 locations are not used. If the window size is 8 x 4,
the top 32 locations will also contain redundant data, and if
the size is 4 x 4 the top 48 will be redundant.
HOST CONTROL LINES
X7:0
8 bit data bus. In a single device system this bus is
bi-directional; in other configurations it is an input.
Only a SINGLE or MASTER device is connected
directly to the host. Other devices receive data from
the output of the previous device in the chain.
7 bit address bus which is used to identify one of
the 73 internal registers. Connected in the same
manner as X7:0.
X15 must be open circuit on the MASTER device
X14:8
X15
11
MITEL [ MITEL NETWORKS CORPORATION ]
