PDSP16488A MA
CE DS R/W PC0 PC1 RE CS3:0
S
MULTI PURPOSE
DATA BUS
X15:0
PROG
MASTER
SINGLE
DELOP
IP7:0
BY
PASS
Y
DELAY
1
LINE
DELAY
CONTROL
X
DELAY
CONTROL
REGISTERS
COEFFICIENT
STORE (64)
COMPARATOR
BIN
3
LINE
DLYS
L7:0
Y
DELAY
4
LINE
DLYS
8X8
ARRAY OF
MAC'S
OVER
FLOW
SCALER
ADDER
D15:0
DATA
OUT
MUX
OEN
CLOCK
Fig. 2 Functional Block Diagram
PIN NO
FUNCTION
AC PACKAGE
A1
B1
C2
C1
D2
D1
E2
E1
F2
G2
G1
H2
J1
J2
K1
K2
L1
L2
M1
N1
N2
L0
F1
L1
L2
L3
SPARE
L4
L5
L6
L7
IP7
SPARE
IP6
IP5
IP4
SPARE
IP3
IP2
IP1
IP0
BYPASS
PIN NO
FUNCTION
AC PACKAGE
X15
M3
X14
N3
X13
M4
SPARE
N4
SINGLE
M5
X12
N5
X11
M6
MASTER
M7
X10
N7
X9
M8
X8
N9
X7
M9
X6
N10
X5
M10
X4
N11
X3
M11
X2
N12
X1
N13
X0
M13
DELOP
L12
PC0
L13
PIN NO
AC PACKAGE
K12
K13
J12
J13
H12
G12
G13
F12
E13
E12
D13
D12
C13
C12
B13
A13
A12
B11
A11
B10
A10
FUNCTION
RES
CS0
CS1
CS2
CS3
PROG
DS
CE
R/W
HRES
OV
PC1
BIN
OEN
D0
D1
D2
D3
D4
D5
D6
PIN NO
FUNCTION
AC PACKAGE
B9
D7
A9
D8
B8
CLK
B7
SPARE
A7
D9
B6
D10
A5
D11
B5
SPARE
A4
D12
B4
D13
A3
D14
B3
D15
A2
F0
F1
VDD
N6
VDD
F13
VDD
A6
VDD
H1
GND
N8
GND
H13
GND
A8
GND
Pin out Table (84 pin PGA - AC84)
2
MITEL [ MITEL NETWORKS CORPORATION ]
