PDSP16256
SPEED MODE 0
(Data input and output at f
SCLK
) CR14:13 = 00, CR12 = 0. CLKOP held high.
SCLK
1
2
3
16
17
18
31
32
33
34
35
FEN
DA15:0
F31:0
CLKOP
A
B
C
A′
B′
C′
A′′
B′′
C′′
D′′
E′′
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 16
Valid result contains
the first 16 data points
available after edge 31
SPEED MODE 1
(Data input and output at half f
SCLK
) CR14:13 = 01, CR12 = 0
SCLK
1
2
3
16
17
18
78
79
80
81
82
FEN
DA15:0
F31:0
CLKOP
A
B
A′
B′
A′′
B′′
C′′
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 16
Valid result contains
the first 32 data points
available after edge 78
SPEED MODE 2
(Data input and output at a quarter f
SCLK
) CR14:13 = 10, CR12 = 0
SCLK
1
2
3
4
5
20
21
22
23
24
272 273 274 275 276
FEN
DA15:0
F31:0
CLKOP
A
B
A′
B′
A′′
B′′
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 20
Valid result contains
the first 64 data points
available after edge 272
SPEED MODE 3
(Data input and output at an eighth f
SCLK
) CR14:13 = 11, CR12 = 0
SCLK
1
2
3
4
5
6
7
8
9
24
25
26
27
28
29
30
31
32
1040 1041 1042 1043
FEN
DA15:0
F31:0
CLKOP
A
B
A′
B′
A′′
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 24
Valid result contains
the first 128 data points
available after edge 1040
SPEED MODE 1 Decimating
(Data input at half f
SCLK
and output at a quarter f
SCLK
) CR14:13 = 01, CR12 = 1.
SCLK
1
2
3
18
19
20
21
22
142
143
144
145
FEN
DA15:0
F31:0
CLKOP
A
B
B′
B′′
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 18
Valid result contains
the first 64 data points
available after edge 142
Figure. 7 Single Filter timing diagrams
8
MITEL [ MITEL NETWORKS CORPORATION ]
