PDSP16256
Loading Coefficients
Filter Control
Two control modes are available selected by input
signal FRUN. In EPROM load mode, when FRUN is
tied high the device will commence operation once the
coefficients have been loaded. The CLKOP signal
indicateswhennewinputdataisrequiredandthatnew
results are available, see Fig. 7. In both EPROM and
remote master load modes, when FRUN is tied low
filteroperationwillnotcommenceuntilahighhasbeen
detected on signal FEN. This mode allows synchroni-
sationtoanexistingdatastream. FENshouldbetaken
high when the first valid data sample is available so
that both are read into the device on the next SCLK
rising edge. Proper device operation requires FEN to
be low during control register and coefficient loading
bothinEPROMmodeandRemoteMastermode.After
loading coefficients, filter operation is determined by
FRUN and FEN as described above.
When the device is to operate in a stand alone
application then the coefficients can be down loaded
as a complete set from a previously programmed
EPROM. Alternatively if the system contains a micro-
processor they can be individually transferred from a
remote master under software control. In any mode
the system clock must be present and stable during
the transfer, and the addressing scheme is such that
the least significant address specifies the coefficient
applied to the first multiplier seen by incoming data.
The addresses used during the load operation are
those illustrated in Fig. 15. The Control Register is
loaded when CCS is high. In byte mode address A0 is
used to select the portion of control register loaded,
otherwise the address bits are redundant. When an
EPROM is used to provide coefficients, this redun-
dancy causes the number of locations needed for any
device to be double that for the coefficients alone.
During device reset
must be held low for a mini-
RES
mum of 16 SCLK cycles. After a reset the control
register returns to its default state of 8C80 HEX. This
places the device into the following mode :
Auto EPROM LOAD
When
is tied low, the PDSP16256 assumes
EPROM
the role of a master device in the system and controls
the loading of coefficients from an external EPROM,
see Fig.15. A load sequence commences when
●
Single filter
Sample rate equal to the clock rate
Non-decimating
A single device (Not in a cascade chain)
●
●
the
input goes high, and will continue until every
RES
●
coefficient has been loaded. BUSY goes high to
indicate that a load sequence is occurring and the
filter output is invalid. The device will not commence
a filter operation until the FEN edge is received after
BUSYhasgonelow.Thisrequirementcanbeavoided
if FRUN is tied high.
●
Bank swap selected by bit in the control register
Coeficient Bank Swap
A Bank Swap feature is provided which allows all
coefficients to be simultaneously replaced with a dif-
ferent set. A bit in the Control Register (CR7) allows
the swap to be controlled by either input signal SWAP
or Control Register bit (CR6). The latter is useful if the
device is controlled by a microprocessor, when driving
a separate pin would entail additional address decod-
ing logic and an external latch.
The address bus pins become outputs on the Master
device,andproduceanewaddresseveryfoursystem
clock periods. This four clock interval, minus output
delays and the data set up time, defines the available
EPROM access time.
The coefficients are always loaded as bytes. The
state ofb the
pin on the master device is ig-
BYTE
If SWAP or bit CR6 is low, the coefficients used will be
those loaded into the lower banks illustrated in Fig. 14.
When the SWAP or CR6 is high, the upper banks are
used.
nored. This arrangement also allows the eight most
significant coefficient bus pins (C15:8) to be used for
other purposes as described later. Since the 16-bit
coefficients are loaded in two bytes the A0 pin speci-
fies the required byte. The maximum number of
stored coefficients is 128, eight address outputs are
therefore provided for the EPROM. These eight out-
puts from the Master must also drive the address
inputs on the slave devices.
The actual swap will occur when the next sampling
clock active going transition occurs. This can be up to
seven system clocks later than the swap transition,
and is filter length dependent. The first valid filtered
output will then occur after the pipeline latencies given
in Tables 3 and 4.
13
MITEL [ MITEL NETWORKS CORPORATION ]
