PDSP16116
t
CLK
CLK
t
CP
OUTPUT P PORTS
VALID DATA
t
CLKH
t
CLKL
VALID DATA
t
CSFTA
OUTPUT SFTA1:0
INPUT DATA X AND Y
t
CSFTA
t
DS
t
DH
t
CES
INPUT CONTROLS CEX AND CEY
t
CONS
INPUT CONTROLS CONX AND CONY
t
WS
INPUT CONTROL WTB1:0
t
CEH
t
CONH
t
WH
Fig. 9 Normal mode timing
OER AND OEI
t
OPLZ
OUTPUT P PORTS
HIGH Z
t
OPZL
HIGH Z
t
OPZH
t
OPHZ
HIGH Z
Fig. 10 Output tristate timing
Test
Delay from
output high
to output
high Z (t
OPHZ
)
Delay from
output low
to output
high Z (t
OPLZ
)
Delay from
output high Z
to output low
(t
OPZL
)
Delay from
output high Z
to output high
(t
OPZH
)
Waveform measurement level
V
H
0·5V
V
T
= 0V
V
T
= V
DD
V
L
1·5V
0·5V
1·5k
V
T
DUT
30p
0·5V
Three state delay measurement load
1·5V
0·5V
V
H
is the voltage reached when the output is driven high
VL is the voltage reached when the output is driven low
Fig. 11 Three state delay measurement
12
MITEL [ MITEL NETWORKS CORPORATION ]
