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PDSP16318A 参数 Datasheet PDF下载

PDSP16318A图片预览
型号: PDSP16318A
PDF下载: 下载PDF文件 查看货源
内容描述: 复杂的累加器 [Complex Accumulator]
分类和应用:
文件页数/大小: 8 页 / 136 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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PDSP16318/16318A
Fig. 3 Block diagram
FUNCTIONAL DESCRIPTION
The PDSP16318 is a Dual 20-bit Adder/Subtractor
configured to support Complex Arithmetic. The device may be
used with each of the adders allocated to real or imaginary
data (e.g. Complex Conjugation), the entire device allocated
to Real or Imaginary Data (e.g. Radix 2 Butterflys) or each of
the adders configured as accumulators and allocated to real
or imaginary data (Complex Filters). Each of these modes
ensures that a full 20MHz throughput is maintained through
both adders, the first and last mode illustrating true Complex
operation, where both real and imaginary data is handled by
the single device.
Both Adder/Subtractors may be controlled
independently via the ASR and ASI inputs. These controls
permit A + B, A - B, B - A or pass A operations, where the A
input to the Adder is derived from the input multiplexer. The
CLR
control line allows the clearing of both accumulator
registers. The two multiplexers may be controlled via the MS
inputs, to select either new input data, or fed-back data from
the accumulator registers. The PDSP16318 contains an 8-
cycle deskew register selected via the DEL control. This
deskew register is used in FFT applications to ensure correct
phasing of data that has not passed through the PDSP16112
Complex Multiplier.
The 16-bit outputs from the PDSP16318 are derived from
the 20-bit result generated by the Adders. The three bit S2:0
input selects eight different shifted output formats ranging
from the most significant 16 bits of the 20-bit data, to the least
significant 13 bits of the 20-bit data. In this mode the 14th, 15th
and 16th bits of the output are set to zero. The shift selected
is applied to both adder outputs, and determines the function
of the OVR flag. The OVR flag becomes active when either of
the two adders produces a result that has more significant
digits than the MSB of the 16-bit output from the device. In this
manner all cases when invalid data appears on the output are
flagged.
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