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NWK954CG 参数 Datasheet PDF下载

NWK954CG图片预览
型号: NWK954CG
PDF下载: 下载PDF文件 查看货源
内容描述: Quad快速以太网中继 [QUAD FAST ETHERNET REPEATER]
分类和应用: 中继器以太网以太网:16GBASE-T
文件页数/大小: 17 页 / 179 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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NWK954
LED Drivers
Signal
COLLED_N
P0_RXLED_N
Pin no.
109
124
Type
Standard
digital output
Standard
digital output
Standard
digital output
Standard
digital output
Standard
digital output
Standard
digital output
Standard
digital output
Standard
digital output
Standard
digital output
Standard
digital outputs
Description
Collision LED.
Drives an LED to indicate that a collision
has occurred either locally or elsewhere in the stack.
Port 0 activity LED.
Drives an LED to indicate link/activity
on port 0. The LED is turned on when a link is established
and flashes off when a packet is being received.
Port 1 activity LED.
Drives an LED to indicate link/activity on
port 1. The LED is turned on when a link is established and
flashes off when a packet is being received.
Port 2 actlvlty LED.
Drives an LED to indicate link/activity on
port 2. The LED is turned on when a link is established and
flashes off when a packet is being received.
Port 3 activlty LED.
Drives an LED to indicate link/activity on
port 3. The LED is turned on when a link is established and
flashes off when a packet is being received.
Port 0 error LED.
Drives an LED to indicate an error on
port 0. See the text for a full description.
Port 1 error LED.
Drives an LED to indicate an error on
port 1. See the text for a full description.
Port 2 error LED.
Drives an LED to indicate an error on
port 2. See the text for a full description.
Port 3 error LED.
Drives an LED to indicate an error on
port 3. See the text for a full description.
Utilization LEDs.
Drives 5 LEDs to indicate utilization of the
network segment. See the text for a full description.
P1_RXLED_N
122
P2_RXLED_N
120
P3_RXLED_N
118
P0_ERLED_N
P1_ERLED_N
P2_ERLED_N
P3_ERLED_N
ACTLED_N4
ACTLED_N3
ACTLED_N2
ACTLED_N1
ACTLED_N0
123
121
119
117
116
115
114
113
112
Table 6
Clocks and Controls
Signal
TXCLKIN
RESET_N
Pin no.
86
5
Type
Digital input
no pull-up
Open drain
digital output and
digital input,
no pull-up
Digital inputs
with pull-ups
Description
25MHz reference clock.
Supplied from an external source
to all NWK954s on the local expansion bus.
Asynchronous reset. This signal is driven low by the on-
chip power-on reset circuit, but may also be driven low
externally for manual reset. Must be pulled high by an
external 5kΩ resistor.
Power-savlng enables.
11 enables power-saving on all
ports. 01 suppresses power saving on port 0, 10
suppresses power saving on port 3, 00 suppresses power-
saving on all ports.
Scrambler seed.
Each ot the four PHY modules in the
NWK954 is provided with a unique scrambler seed derived
from TA[4:2]. To ensure that all ot the local PHYs have
unique scrambler seeds, each NWK954 connected to the
local expansion bus should have its TA[4:2] input set to a
unique value by connecting to DIGVDD or DIGGND.
PSEN0
PSEN1
87
88
TA4
TA3
TA2
13
14
15
Digital inputs,
no pull-ups
Table 7
11