NWK914D
Pin Name
SYMBOL Interface
RXC
SDT
TDAT4
TDAT3
TDAT2
TDAT1
TDAT0
TXC
RDAT0
RDAT1
RDAT2
RDAT3
RDAT4
Network Interface
RXIP
RXIN
TXON
TXOP
Pin Type
Pin Number
Pin Description
TTLOP
TTLOP
TTLIP
TTLIP
TTLIP
TTLIP
TTLIP
TTLOP
TTLOP
TTLOP
TTLOP
TTLOP
TTLOP
analog input
analog input
analog output
analog output
4
5
40
41
42
43
44
47
48
49
50
51
52
15
16
22
23
25MHz recovered receive clock. This is aligned with and used to clock
out the 5 bit parallel receive data to the PCS layer.
Signal detect output. This output is high when an input signal of sufficient
amplitude is detected on the RXI inputs.
The 100BASE-TX transmit input bit 4
The 100BASE-TX transmit input bit 3
The 100BASE-TX transmit input bit 2
The 100BASE-TX transmit input bit 1
The 100BASE-TX transmit input bit 0
25MHz transmit clock. This is aligned with and used to clock in the 5 bit parallel
100BASE-TX transmit data from the PCS layer.
The 100BASE-TX receive output bit 0
The 100BASE-TX receive output bit 1
The 100BASE-TX receive output bit 2
The 100BASE-TX receive output bit 3
The 100BASE-TX receive output bit 4
+ Differential receive signal input from magnetics
– Differential receive signal input from magnetics
– Differential transmit line driver outputs to magnetics
+ Differential transmit line driver outputs to magnetics
10BASE-T Interface
10TXIN
analog input
10TXIP
analog input
Control Pins
N10/100
TTLIP
19
20
36
The filtered 10BASE-T transmit input (–)
The filtered 10BASE-T transmit input (+)
10/100 mode selection. A low selects the 10BASE-T mode and enables the
data on pins 10TXIP/N to be outut on the TXOP/N pins. A high selects the
100BASE-TX mode, enabling the 100Mb/s drivers.
Mode select input for equalizer. Normally this pin is left unconnected (floating) for
auto-eq. mode. High selects minimum equalization. Low selects full equalization.
Loopback enable input. A high on this pin selects the loopback mode and low selects
normal operation.
Transmit output enable. A high on this pin selects normal operation. A low on this
pin puts both of the TX drivers in tri-state mode.
Test pin. This pin must be left unconnected for proper operation.
Test pin. This pin must be left unconnected for proper operation.
No connection. This pin must be left unconnected for proper operation.
25MHz clock input. An external 25MHz oscillator is input to this pin.
TXOP/N line driver current setting pin. Connects to TXGND through a resistor.
Differential loop filter pin for receive PLL (see fig.6)
Differential loop filter pin for receive PLL (see fig.6)
Differential loop filter pin for transmit clock PLL (see fig.6)
Differential loop filter pin for transmit clock PLL (see fig.6)
GND for TTL logic I/Os
+5V supply to receive logic
GND to receive PLL
+5V supply to receive PLL
+5V supply to adaptive equalizer and QFB circuits
GND to to adaptive equalizer and QFB circuits
+5V supply to MLT-3 to NRZI converter
+5V supply to transmit line driver circuits
GND to transmit line driver circuits
+5V supply to on-chip bandgap reference
Chip substrate GND connection
GND to on-chip bandgap reference
GND to to transmit clock-multiplier PLL
+5V supply to transmit clock-multiplier PLL
+5V supply to transmit logic
+5V supply to TTL logic I/Os
EQSEL
LBEN
TXOE
TESTIP
TEST
N/C
3 level IP
TTLIP
TTLIP
test
test
18
35
33
37
38
2,3,7,8
45
25
10
11
30
31
1,39
6
9
12
13
14
17
21
24
26
27
28
29
32
34
46
Component Connections
REFCLK
TTLIP
TXREF
analog input
LFRB
analog
LFRA
analog
LFTB
analog
LFTA
analog
Power
TTLGND
RDLV
CC
RXPLLGND
RXPLLV
CC
RXV
CC
2
RXGND
RXV
CC
1
TXV
CC
TXGND
RXV
CC
SUBGND
BGAPGND
TXPLLGND
TXPLLV
CC
TDLV
CC
TXLV
CC
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Table 1: Pin descriptions
6
MITEL [ MITEL NETWORKS CORPORATION ]
