Advance Information
t
BCL
t
F
MT91L62
t
BCLH
t
R
CLOCKin
70%
(BCL)
30%
t
BCLL
t
DIS
Din
70%
30%
t
DOZL
Dout
70%
30%
t
DOZH
t
SSS
STB
70%
30%
t
ENW
t
SSH
t
DOLZ
t
DOHZ
t
DD
t
DIH
NOTE: Levels refer to % V
DD
(CMOS I/O)
Figure 5 - SSI Synchronous Timing Diagram
AC Electrical Characteristics
†
- SSI BUS Asynchronous Timing (note 1) (see Figure 6)
Characteristics
1 Bit Cell Period
2 Frame Jitter
3 Bit 1 Dout Delay from STB
going high
4 Bit 2 Dout Delay from STB
going high
5 Bit n Dout Delay from STB
going high
Sym
T
DATA
T
j
t
dda1
t
dda2
t
ddan
600+
T
DATA
-T
j
600 +
(n-1) x
T
DATA
-T
j
T
DATA
-T
j
T
DATA
\2
+500ns-T
j
+(n-1) x
T
DATA
T
DATA
\2
+500ns+T
j
+(n-1) x
T
DATA
600+
T
DATA
600 +
(n-1) x
T
DATA
Min
Typ
‡
7812
3906
600
T
j
+600
600 +
T
DATA
+T
j
600 +
(n-1) x
T
DATA
+T
j
T
DATA
+T
j
Max
Units
ns
ns
ns
ns
ns
ns
C
L
=50 pF, R
L
=1K
C
L
=50 pF, R
L
=1K
C
L
=50 pF, R
L
=1K
n=3 to 8
Test Conditions
BCL=128 kHz
BCL=256 kHz
6 Bit 1 Data Boundary
7 Din Bit n Data Setup time from
STB rising
T
DATA1
t
SU
ns
ns
n=1-8
8 Din Data Hold time from STB
rising
t
ho
ns
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1:Not production tested, guaranteed by design.
7-183
MITEL [ MITEL NETWORKS CORPORATION ]
