Advance Information
Overview
The 3V Single-Rail Codec features complete Analog/
Digital and Digital/Analog conversion of audio
signals (Filter/Codec) and an analog interface to a
standard analog transmitter and receiver (analog
Interface). The receiver amplifier is capable of
driving a 20k ohm load.
MT91L62
Companding law selection for the Filter/Codec is
provided by the A/µ companding control pin. Table
1 illustrates these choices.
ITU-T (G.711)
µ-Law
1000 0000
1111 1111
0111 1111
0000 0000
Code
+ Full Scale
+ Zero
A-Law
1010 1010
1101 0101
0101 0101
0010 1010
Functional Description
Filter/Codec
The Filter/Codec block implements conversion of the
analog 0-3.3 kHz speech signals to/from the digital
domain compatible with 64 kb/s PCM B-Channels.
Selection of companding curves and digital code
assignment are programmable. These are ITU-T
G.711 A-law or
µ-Law,
with true-sign/Alternate Digit
Inversion.
The Filter/Codec block also implements a transmit
audio path gain in the analog domain. Figure 3
depicts the nominal half-channel for the MT91L62.
The internal architecture is fully differential to provide
the best possible noise rejection as well as to allow a
wide dynamic range from a single 3 volt supply
design. This fully differential architecture is
continued into the Analog Interface section to
provide full chip realization of these capabilities for
the external functions.
A reference voltage (V
Ref
), for the conversion
requirements of the Codec section, and a bias
voltage (V
Bias
), for biasing the internal analog
sections, are both generated on-chip. V
Bias
is also
brought to an external pin so that it may be used for
biasing external gain setting amplifiers. A 0.1µF
capacitor must be connected from V
Bias
to analog
ground at all times. Likewise, although V
Ref
may only
be used internally, a 0.1µF capacitor from the V
Ref
pin to ground is required at all times. The analog
ground reference point for these two capacitors must
be physically the same point. To facilitate this the
V
Ref
and V
Bias
pins are situated on adjacent pins.
The transmit filter is designed to meet ITU-T G.714
specifications. An anti-aliasing filter is included. This
is a second order lowpass implementation with a
corner frequency at 25 kHz.
The receive filter is designed to meet ITU-T G.714
specifications. Filter response is peaked to
compensate for the sinx/x attenuation caused by the
8 kHz sampling rate.
-Zero
(quiet code)
- Full Scale
Table 1: Law Selection
Analog Interfaces
Standard interfaces are provided by the MT91L62.
These are:
• The analog inputs (transmitter), pins AIN+/AIN-.
The maximum peak to peak input is 2.123Vpp
µ−law
across AIN+/AIN-
and 2.2Vpp A-law
across these pins.
• The analog outputs (receiver), pins AOUT+/
AOUT-. This
internally
compensated
fully
differential output driver is capable of driving a
load of 20k ohms.
PCM Serial Interface
A serial link is required to transport data between the
MT91L62 and an external digital transmission
device. The MT91L62 utilizes the strobed data
interface found on many standard Codec devices.
This interface is commonly referred to as Simple
Serial Interface (SSI).
The bit clock rate is selected by setting the CSL2-0
control pins as shown in Figure 2.
Quiet Code
The PCM serial port can be made to send quiet code
to the decoder and receive filter path by setting the
RxMute pin high. Likewise, the PCM serial port will
send quiet code in the transmit path when the
7-175
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