Advance Information
MT91L60/61
tBCL
tBCLH
tR
tF
CLOCKin
(BCL)
70%
30%
tBCLL
tDIS
tDIH
70%
30%
Din
tDD
tDOZL
70%
30%
Dout
tDOZH
tDOLZ
tDOHZ
tSSH
tENW
tSSS
70%
30%
STB
tDSTBF
tDSTBR
70%
30%
STBd
tENWD
NOTE: Levels refer to % VDD (CMOS I/O)
Figure 12 - SSI Synchronous Timing Diagram
AC Electrical Characteristics† - SSI BUS Asynchronous Timing (note 1) (see Figure 13)
‡
Characteristics
1 Bit Cell Period
Sym
Min
Typ
Max
Units
Test Conditions
TDATA
7812
3906
ns
ns
BCL=128 kHz
BCL=256 kHz
2 Frame Jitter
Tj
600
ns
ns
3 Bit 1 Dout Delay from STB
going high
tdda1
Tj+600
CL=50 pF, RL=1K
CL=50 pF, RL=1K
4 Bit 2 Dout Delay from STB
going high
tdda2
tddan
600+
TDATA-Tj
600+
TDATA
600 +
TDATA+Tj
ns
ns
5 Bit n Dout Delay from STB
going high
600 +
(n-1) x
600 +
(n-1) x
TDATA
600 +
(n-1) x
CL=50 pF, RL=1K
n=3 to 8
T
DATA-Tj
T
DATA+Tj
6 Bit 1 Data Boundary
TDATA1
tSU
TDATA-Tj
TDATA+Tj
ns
ns
7 Din Bit n Data Setup time from
STB rising
TDATA\2
+500ns-Tj
+(n-1) x
TDATA
n=1-8
8 Din Data Hold time from STB
rising
tho
TDATA\2
+500ns+Tj
+(n-1) x
TDATA
ns
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.
25
MITEL [ MITEL NETWORKS CORPORATION ]
