Advance Information
Pin Description (continued)
Pin #
22
11
12
13
14
24
12
13
14
15
28
14
15
16
17
Name
V
SS
Negative Power Supply
(0V).
Description
MT9171/72
DSTo/Do
Data ST-BUS Out/Data Out
(Digital). A 2.048 Mbit/s serial PCM/data output in
DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.
DSTi/Di
Data ST-BUS In/Data In
(Digital). A 2.048 Mbit/s serial PCM/data input in DN
mode. In MOD mode this is a continuous bit stream at the bit rate selected.
F0o/RCK
Frame Pulse Out/Receive Bit Rate Clock
output (Digital). In DN mode a 244 ns
wide negative pulse indicating the end of the active channel times of the device
to allow daisy chaining. In MOD mode provides the receive bit rate clock to the
system.
C4/TCK
Data Clock/Transmit Baud Rate Clock
(Digital). A 4.096 MHz TTL compatible
clock input for the MASTER and output for the SLAVE in DN mode. For MOD
mode this pin provides the transmit bit rate clock to the system.
Oscillator Output.
CMOS Output.
Oscillator Input.
CMOS Input. D.C. couple signals to this pin. Refer to D.C.
Electrical Characteristics for OSC1 input requirements.
Precanceller Disable.
When held to Logic ’1
’,
the internal path from L
OUT
to the
precanceller is forced to V
Bias
thus bypassing the precanceller section. When
logic ’0’, the L
OUT
to the precanceller path is enabled and functions normally. An
internal pulldown (50 kΩ) is provided on this pin.
No Connection.
Leave open circuit
15
16
19
16
17
18
17
19
20
21
22
23
OSC2
OSC1
Precan
8,
18
1,6,
11,
18,
20,
25
24
NC
19
21
L
OUT
DIS
L
OUT
Disable.
When held to logic “1”, L
OUT
is disabled (i.e., output = V
Bias
). When
logic “0”, L
OUT
functions normally. An internal pulldown (50 kΩ) is provided on this
pin.
TEST
L
IN
V
DD
Test Pin.
Connect to V
SS
.
Receive Signal
input (Analog).
Positive Power Supply
(+5V) input.
20
21
22
22
23
24
26
27
28
9-135