欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT9171AN 参数 Datasheet PDF下载

MT9171AN图片预览
型号: MT9171AN
PDF下载: 下载PDF文件 查看货源
内容描述: ISO2 -CMOS ST- BUS⑩家庭数字用户接口电路数字网络接口电路 [ISO2-CMOS ST-BUS⑩ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit]
分类和应用: 网络接口电信集成电路光电二极管综合业务数字网
文件页数/大小: 22 页 / 396 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
 浏览型号MT9171AN的Datasheet PDF文件第3页浏览型号MT9171AN的Datasheet PDF文件第4页浏览型号MT9171AN的Datasheet PDF文件第5页浏览型号MT9171AN的Datasheet PDF文件第6页浏览型号MT9171AN的Datasheet PDF文件第8页浏览型号MT9171AN的Datasheet PDF文件第9页浏览型号MT9171AN的Datasheet PDF文件第10页浏览型号MT9171AN的Datasheet PDF文件第11页  
Advance Information
In DIGITAL NETWORK (DN) mode, upon entering
the DNIC from the DV and CD ports, the B-channel
data, D-channel D0 (and D1 for 160 kbit/s), the HK
bit of the C-channel (160kbit/s only) and a SYNC bit
are combined in a serial format to be sent out on the
line by the Transmit Interface (Figures 11, 12). The
SYNC bit produces an alternating 1-0 pattern each
frame in order for the remote end to extract the frame
alignment from the line. It is possible for the remote
end to lock on to a data bit pattern which simulates
this alternating 1-0 pattern that is not the true SYNC.
To decrease the probability of this happening the
DNIC may be programmed to put the data through a
prescrambler that scrambles the data according to a
predetermined polynomial with respect to the SYNC
bit. This greatly decreases the probability that the
SYNC pattern can be reproduced by any data on the
line. In order for the echo canceller to function
correctly, a dedicated scrambler is used with a
scrambling algorithm which is different for the SLV
and MAS modes. These algorithms are calculated in
such a way as to provide orthogonality between the
MT9171/72
near and far end data streams such that the
correlation between the two signals is very low.
For any two DNICs on a link, one must be in SLV
mode with the other in MAS mode. The scrambled
data is differentially encoded which serves to make
the data on the line polarity-independent. It is then
biphase encoded as shown in Figure 10. See “Line
Interface” section for more details on the encoding.
Before leaving the DNIC the differentially encoded
biphase data is passed through a pulse-shaping
bandpass transmit filter that filters out the high and
low frequency components and conditions the signal
for transmission on the line.
The composite transmit and receive signal is
received at L
IN
. On entering the DNIC this signal
passes through a Precanceller which is a summing
amplifier and lowpass filter that partially cancels the
near-end signal and provides first order antialiasing
for the received signal. Internal, partial cancellation
F0
C4
A AA
AAAAAA
AAAAA
AAAAAAAAAAA AAAAAAAA
AAAAAAAAAAAAAAAAAAAAA
AAAA
AA
AAAAAAAAAAAAA AAAAAAAAAA
A
AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAA
AA AAAAAAAA
AA
AAAAA
A AA
AAAAAAAAAAA AAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAA AAAAAAAAA
AAAAAAAAAAAAA
AA
A
AAAA
AA
A AA
AAAAAAAAAAAA
AA
A
AAAAAAAAAAAAA
AA AAAAAAAA
A
AA
CDSTo
AAAAA
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
AAAAAAAAAAA AAAAAAAA
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
AAAAAAAAAAAAAAAAAAAAAAAA
C
0
A AA
AAAAA
AAAAAAAAAAA AAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAA
AA
A
AA
A AA
AAAAA
AAAAAAAAAAA AAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAA
AA
A
AA
A AA
AAAAA
AAAAA
AAAAAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAAAAA
AAAA
AA
A
AA
A A
AAAAAAAAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAA
AAAAAAAAAAAA
A
A AA
AAAAA
AAAAAAAAAAAA
AA
A
AAAAAAAAAAAAA
AA AAAAAAAA
A AA
AA
A
AAAAAAAAAAAAA
AA
AA
AAAAA
C C C C C C C C
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAA AAAAAAAA
D D D D D D D D
AAAAAAAAAAAAAAAAAAAAAAAA
C
AAAAAAAAAAAA
AAAAAAAAAAAAA AAAAAAAAAA
A
AAAA
A AA
AAAA
AA
A
AAAAAAAAAAAAA
AA AAAAAAAA
AA
CDSTi
AAAAA
0
1
2
3
4
5
6
7
AAAAAAAAAAA AAAAAAAA
0
1
2
3
4
5
6
7
AAAAAAAAAAAAAAAAAAAAAAAA
0
A AA
AAAAA
AAAAAAAAAAA AAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAA AAAAAAAAA
AAAAAAAAAAAAA
AA
A
AAAAAAAAAAAA
A AA
AAAAA
AAAAAAAAAAA AAAAAAAA
AAAA
AA
A
AAAAAAAAAAAAAAAA AAAAA
AAAAAAAA AA
AA
A
AA
A AA
AAAAA
AAAAAAAAAAA
AAAA
AA
AAAAAAAAAAAAAA
A
AAAA
AA
F0o
3.9
µsec
62.5
µsec
125
µsec
Channel Time 0
Channel Time 16
Figure 7 - CD Port (Modes 2,6)
CLD
TCK
CDi
C
6
C
7
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
0
C
1
CDo
C
6
C
7
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
0
C
1
Figure 8 - CD Port (Modes 1,5)
9-139