Preliminary Information
MT9126
MCLK
F0i
ENB2/F0od
C2o
EN1 (output)
EN2 (output)
0 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
PCMi1
D
C
B1
B2
P
C
M
0 1
7 6 5 4 3 2 1 0
SEL=0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
PCMo1
PCMi2
PCMo2
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
B
y
p
a
s
s
SEL=1
B3
B4
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
0 1
0 1
7 6 5 4 3 2 1 0
C
7 6 5 4 3 2 1 0
B1/B3
7 6 5 4 3 2 1 0
B2/B4
ADPCMi
ADPCMo
D
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
B1
B2
x x x 1 2 3 4
7 6 5 4 3 2 1 0
C
x
1 2 3 4
0
x x x x
x x x x
1
PCMi/o1
PCMi/o2
D
B3
B4
x x x x
A
D
P
C
M
1 2 3 4
1 2 3 4
7 6 5 4 3 2 1 0
C
1 2 3 4 1 2 3 4
B1 B2
1 2 3 4 1 2 3 4
B3 B4
0 1
ADPCMi/o
32 kb/s
24 kb/s bit 4 = X
D
B
y
p
a
s
s
SEL=0
SEL=1
D
C
B1 B2 B3 B4
1 2 1 2 1 2 1 2
B1 B2 B3 B4
1 2 1 2 1 2 1 2
ADPCMi/o
(16 kb/s)
7 6 5 4 3 2 1 0
0 1
0 1
B1
B2
PCMi/o1
PCMi/o2
1 2 x x x x x x
1 2 x x x x x x
7 6 5 4 3 2 1 0
C
D
B3
B4
1 2 x x x x x x
1 2 x x x x x x
outputs = High impedance
inputs = don’t care
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel boundaries
Two frame delay from data input to data output
Figure 9 - ST-BUS PCM and ADPCM Bypass Relative Timing
8-45
MITEL [ MITEL NETWORKS CORPORATION ]
