CMOS MT9080
Switching any input channel to an output channel
timeslot is possible by merely writing the address of
the input channel in the Connection Memory location
corresponding to the output channel timeslot. For
example, to switch channel 1 to output channel 5
and enable output drivers during channel 5, the
Connection Memory location corresponding to
channel 5 should be loaded with Hex 2001. This
word will be clocked out of the Connection Memory
during timeslot 4 and will cause the Data Memory to
clock out contents of the memory corresponding to
channel 1 during the channel 5 timeslot. The 16 bit
word clocked out by the Connection Memory will also
enable Data Memory output drivers, and, external
drivers.
2048 Channel Switch Matrix
A
2048 channel, double buffered timeslot
interchange switch can be constructed with three
SMXs as shown in Figure 18. SMX#1 and SMX#2
are used to store data and switch it in time, while the
third SMX functions as a Connection Memory.
SMX#1 and 2 are operated in the Counter Mode and
External Mode alternatively in consecutive frames.
In any specific frame, one of the two is in Counter
mode while the other is in External mode. The
functions are reversed in the successive frame. The
SMX in counter mode is programmed to write data
CNT/EXT
SMX #1
CNT/EXT
SMX #2
16
16
C16
16
+5
16
Data
Output
D0-D15o
Mx
D0-D15o
Mx
D0-D15i
CK
D0-D15i
CK
+5
C16
DATA
MEMORY
DATA
MEMORY
My
CS
DS
My
CS
DS
FP
FP
Mz
Mz
R/W
ODE
R/W
ODE
Timing
Generator
A0-A10
A0-A10
ME
ME
DFP
CFP
11
11
U2
C16
16.384 MHz
U1
D11
D0o-D10o
CM-2
SMX #3
+5
ODE
Mz
CONNECTION
MEMORY
FP
CK
My
Mx
C16
MPU Interface
Notes:
1) U1 and U2 are required if the data output bus is to be enabled/disabled via the microprocessor interface.
2) All inputs not shown should be connected to Ground (VSS).
Figure 18 - 2048 Channel Timeslot Interchange Circuit
2-113
MITEL [ MITEL NETWORKS CORPORATION ]
