MT9080B CMOS
CK
FP
Data
CH X
In
CH Y
CH Z
Data
Out
CH X
CH Y
CH Z
t
d
t = (Address x 2) + 2 Clock Cycles
d
Figure 14 - Shift Register Mode Data Input/Output Timing
counter, this word will be clocked out of the memory
on to the data bus (D0 -D15 ).
Applications
o
o
1024 Channel Switch Matrix
The output on the Connect Memory data bus
(D0 -D9 ) is used to specify the Data Memory
o
o
A 1024 channel, non-blocking, timeslot interchange
switch can be constructed using two SMX devices
(refer to Figure 15). One SMX is operated in the Data
Memory mode, while the second device is operated
in Connect Memory Mode-1.
location to be read out during any particular timeslot.
The Connection Memory is programmed in a manner
that permits specific addresses to be output in
certain timeslots. The Data Memory will clock out
data from internal memory locations according to the
address asserted on its address bus. As mentioned
earlier, this address is latched into Data Memory with
a positive edge of the clock. The contents of the
appropriate addressed memory location will be
clocked out of the device at the beginning of the next
channel timeslot.
Data to be switched is clocked into the data memory
via the 16 bit input data bus and stored sequentially
in memory locations addressed by the internal 11 bit
counter. The data is read out of the Data Memory
(SMX#1) according to the external address supplied
by the Connection Memory (SMX#2). The
Connection memory clocks out contents of the
memory according to the addresses supplied by the
internal counter.
Connection Memory bit 10 controls the level on the
ODE input. The ODE pin is used to enable the output
drivers of the Data Memory. The capability to
selectively enable or disable the output drivers
during specific channel timeslots is required when
constructing larger switches using the 1024 channel
switch as a building block.
The clock applied at the CK input of both the devices
has a frequency of 16.384 MHz. There are two clock
periods in each channel timeslot (see Figure 16). A
framing signal (FP) with a frequency of 8 kHz is used
to delineate frames with 1024 channels each. The
FP input to the Data Memory is delayed by seven
clock periods from the Connection Memory frame
pulse. This phase delay synchronizes the internal
counters of the two SMXs such that the Connection
Memory clocks out addresses one channel ahead of
the affected timelsot.
The Message Enable (ME) input of the Data Memory
is controlled by D11. Setting this particular bit high
will result in the data latched into the address bus
being clocked out on to the Data Memory output bus.
Note that only 10 of the 16 address inputs are
actually connected to the data bus of the Connection
Memory. Consequently, only 10 of the 16 data output
bits on the Data Memory can be dynamically
controlled through the Connection Memory. In other
applications, all 16 of the address bits may be
connected to the data output bus of the Connection
Memory.
Using the connections illustrated in Figure 15, the
Data Memory address and control functions can be
mapped onto specific bits of the Connect Memory to
form a 16 bit control word, as shown in Figure 17.
The 16 bit control word is written into the Connection
Memory by the processor. Subsequently, when the
memory location is addressed by the internal
The mode of operation of the Data Memory can be
changed from Data Memory Mode-1 to Data Memory
Mode-2 by setting or resetting D12 in the connection
2-110
MITEL [ MITEL NETWORKS CORPORATION ]
