MT90863
Advance Information
Pin Description (continued)
128 MQFP
Pin#
144 BGA
Pin#
Name
Description
92
B13
C4i/C8i HMVIP/CT Bus Clock (5V Tolerant Input): When HMVIP mode is
enabled, this pin accepts a 4.096MHz clock for HMVIP frame pulse
alignment. When CT Bus mode is enabled, it accepts a 8.192MHz
clock for CT frame pulse alignment.
94
95
A13
C12
F0o
Frame Pulse (5V Tolerant Output): A 244ns wide negative frame
pulse that is phase locked to the master frame pulse (F0i).
C4o
C4 Clock (5V Tolerant Output): A 4.096MHz clock that is phase
locked to the master clock (C16i).
98-105, C11, B12, B11, STio0 - 15 Serial Input Streams 0 to 15 / Frame Evaluation Inputs 0 to 15 (5V
108-115 A12, A11, B10, FEi0 - 15 Tolerant I/O). In 2Mb/s and HMVIP modes, these pins accept serial
A10, B9, A9,
C8, B8, A8, C7,
B7, A7, A6,
TDM data streams at 2.048 Mb/s with 32 channels per stream. In 4Mb/
s or 8Mb/s mode, these pins accept serial TDM data streams at 4.096
or 8.192 Mb/s with 64 or 128 channels per stream respectively. In
Frame Evaluation Mode (FEM), they are frame evaluation inputs.
118-125 B6, A5, B5, A4, STio16 - 23 Serial Input Streams 16 to 23 (5V Tolerant I/O). In 2Mb/s or 4Mb/s
B4, C4, A3, B3 FEi16 - 23 mode, these pins accept serial TDM data streams at 2.048 or 4.096
Mb/s with 32 or 64 channels per stream respectively. In HMVIP mode,
these pins have a data rate of 8.192Mb/s with 128 channels per
stream. In Frame Evaluation Mode (FEM), they are frame evaluation
inputs.
128,
1-7
A2, B2, A1, C3, STio24 - 31 Serial Input Streams 24 to 31 (5V Tolerant I/O). These pins are only
C2, B1, D3, D2
used for 2Mb/s or 4Mb/s mode. They accept serial TDM data streams
at 2.048 or 4.096 Mb/s with 32 or 64 channels per stream respectively.
9
C1
D1
E2
TMS
TDI
Test Mode Select (3.3V Input with internal pull-up): JTAG signal
that controls the state transitions of the TAP controller.
10
11
Test Serial Data In (3.3V Input with internal pull-up): JTAG serial
test instructions and data are shifted in on this pin.
TDO
Test Serial Data Out (3.3V Output): JTAG serial data is output on this
pin on the falling edge of TCK. This pin is held in a high impedance
state when JTAG scan is not enabled.
12
13
E1
F2
TCK
Test Clock (5V Tolerant Input): Provides the clock to the JTAG test
logic.
TRST
Test Reset (3.3 V Input with internal pull-up): Asynchronously
initializes the JTAG TAP controller by putting it in the Test-Logic-Reset
state. This pin should be pulsed low on power-up, or held low
continuously, to ensure that the MT90863 is in the normal operation
mode.
14
15
F3
F1
IC1
Internal Connection 1 (3.3V Input with internal pull-down):
Connect to VSS for normal operation.
RESET Device Reset (5V Tolerant Input): This input (active LOW) puts the
MT90863 in its reset state. This clears the device’s internal counters
and registers. It also brings microport data bus STio0 - 31 and STo0 -
15 to a high impedance state.
16
G3
IC2
Internal Connection 2 (3.3V Input):
Connect to VSS for normal operation.
4
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