MT90863
Advance Information
•
Test Reset (TRST)
Reset the JTAG scan structure. This pin is
internally pulled to VDD.
JTAG Support
The MT90863 JTAG interface conforms to the
Boundary-Scan IEEE1149.1 standard. This stan-
dard specifies a design-for-testability technique
called Boundary-Scan Test (BST). The operation of
the boundary-scan circuitry is controlled by an
external Test Access Port (TAP) Controller.
Instruction Register
The MT90863 uses the public instructions defined in
the IEEE 1149.1 standard. The JTAG Interface
contains a two-bit instruction register. Instructions
are serially loaded into the instruction register from
the TDI when the TAP Controller is in its shifted-IR
state. These instructions are subsequently de-coded
to achieve two basic functions: to select the test data
register that may operate while the instruction is
current; and, to define the serial test data register
path that is used to shift data between TDI and DO
during data register scan-ning.
Test Access Port (TAP)
The Test Access Port (TAP) accesses the MT90863
test functions. It consists of three input pins and one
output pin as follows:
•
Test Clock Input (TCK)
TCK provides the clock for the test logic.
The TCK does not interfere with any on-chip
clock and thus remains independent. The
TCK permits shifting of test data into or out
of the Boundary-Scan register cells
concurrently with the operation of the device
and without interfering with the on-chip
logic.
Test Data Register
As specified in IEEE 1149.1, the MT90863 JTAG
Interface contains three test data registers:
•
The Boundary-Scan Register
The Boundary-Scan register consists of a
series of Boundary-Scan cells arranged to
form a scan path around the boundary of
the MT90863 core logic.
•
Test Mode Select Input (TMS)
The TAP Controller uses the logic signals
received at the TMS input to control test
operations. The TMS signals are sampled at
the rising edge of the TCK pulse. This pin is
internally pulled to Vdd when it is not driven
from an external source.
•
•
The Bypass Register
The Bypass register is a single stage shift
register that provides a one-bit path from
TDI to its TDO.
•
Test Data Input (TDI)
The Device Identification Register
The device identification register is a 32-bit
register. The register contents are:
Serial input data applied to this port is fed
either into the instruction register or into a
test data register, depending on the
sequence previously applied to the TMS
input. Both registers are described in a
subsequent section. The received input data
is sampled at the rising edge of TCK pulses.
This pin is internally pulled to Vdd when it is
not driven from an external source.
MSB
LSB
0000 0000 1000 0110 0011 0001 0100 1011
The LSB bit in the device identification register is
the first bit clock out.
The MT90863 scan register contains 212 bits. Bit 0
in Table 23 Boundary Scan Register is the first bit
clocked out. All tri-state enable bits are active high.
•
Test Data Output (TDO)
Depending on the sequence previously
applied to the TMS input, the contents of
either the instruction register or data
register are serially shifted out towards the
TDO. The data out of the TDO is clocked on
the falling edge of the TCK pulses. When no
data is shifted through the boundary scan
cells, the TDO driver is set to a high
impedance state.
24
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