®
CMOS
MT90810
Flexible MVIP Interface Circuit
Preliminary Information
Features
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MVIP
™
and ST-BUS
™
compliant
MVIP Enhanced Switching with 384x384
channel capacity (256 MVIP channels; 128
local channels)
On-chip PLL for MVIP master/slave operation
Local output clocks of 2.048,4.096,8.192MHz
with programmable polarity
Local serial interface is programmable to
2.048, 4.096, or 8.192Mb/s with associated
clock outputs
Additional control output stream
Per-channel message mode
Two independently programmable groups of up
to 12 framing signals each
Motorola non-multiplexed or Intel multiplexed/
non-multiplexed microprocessor interface
MT90810AK
ISSUE 2
October 1994
Ordering Information
100 Pin PQFP
0 °C to +70 °C
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•
•
Description
Mitel’s MT90810 is a Flexible MVIP Interface Circuit
(FMIC). The MVIP (Multi-Vendor Integration
Protocol) compliant device provides a complete
MVIP compliant interface between the MVIP Bus and
a wide variety of processors, telephony interfaces
and other circuits. A built-in digital time-slot switch
provides MVIP enhanced switching between the full
MVIP Bus and any combination of up to 128 full
duplex local channels of 64kbps each. An 8 bit
microprocessor port allows real-time control of
switching and programming of device configuration.
On-board clock circuitry, including both analog and
digital phase-locked loops, supports all MVIP clock
modes. The local interface supports PCM rates of
2.048, 4.096 and 8.192Mb/s, as well as parallel DMA
through the microprocessor port.
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Applications
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•
•
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Medium size digital switch matrices
MVIP interface functions
Serial bus control and monitoring
Centralized voice processing systems
Voice/Data multiplexer
EX_8KA
EX_8KB
X2
X1/CLKIN PLL_LO
PLL_LI
FRAME
SEC8K
C4b
C2o
F0b
DSo[0:7]
DSi[0:7]
LDO[0:3]
LDI[0:3]
TCK
TMS
TDI
TDO
Timing and Clock Control
(Oscillator and Analog & Digital PLLs)
Enhanced Switch
S-P/
P-S
Data Memory
Connection Memory
Programmable
Framing Signals
CLK2
CLK4
CLK8
RESET
CSTo
FGA[0:11]
FGB[0:11]
JTAG
Microprocessor Interface
ERR
AD[0:7] A[0:1] ALE
WR/
R/W
RD/
DS
CS
RDY/ DREQ[0:1] DACK[0:1]
DTACK
Figure 1 - Functional Block Diagram
2-145
MITEL [ MITEL NETWORKS CORPORATION ]
