CMOS
memory. The delay through the matrix can be
optimized for specific applications by selectively
enabling one of the two modes. Data Memory-1
(DM-1) is designed for voice switching applications
where it is generally desirable to minimize delay
through the switch. As mentioned earlier in the DM-1
description, the delay through the switch depends
upon the difference between the input channel
timeslot and the output channel timeslot.
Consecutive output channels switched from
non-contiguous input channels will not always
originate from the same input frame. For example, if
channels 3, 6 and 8 are to be switched to channels 5,
6 and 7; output channel 5 will contain data input in
the current frame, while channels 6 and 7 will contain
data clocked in one frame earlier. Data Memory-2
MT9080B
(DM-2) is designed for data switching applications
where concatenation of a number of channels is
often necessary. Data clocked out of the device will
originate from the previous frame, regardless of the
input/output time difference. There is one exception,
when channel 1023 is switched to channel 0, the
contents of Channel 0 will not originate from the
previous frame but rather from the frame before it.
The capability to selectively change between DM-1
and DM-2 allows a single switch to handle both voice
and data effectively.
External bus drivers can be controlled with D13 of
the Connection Memory data bus. This bit will be
output along with the remaining bits one channel
SMX #1
DM-1/2
Parallel Input Data
16
D0
i
-D15
i
DATA
MEMORY
D0
o
-D15
o
16
A10-A15
FP
CK
MODE
Parallel Output Data
+5
R/W
CS
DS
A0-A9
ODE
ME
Z
Y
X
FP#1
Timing
Generator
FP#2
CK
10
D0
o
-D9
o
D10
o
D11
o
D12
o
D13
o
External
Tristate
Control
CK
FP
SMX #2
CM-1
CONNECTION
MEMORY
X
MODE
Y
Z
0
1
0
A11-A15
A10
CD
CS
D0-D15
R/W
DTA
DS
A0-A9
+5
Address
Decode
D0-D15
R/W
HALT
DS
IRQ
16-BIT MPU
Note: All other inputs not shown in this diagram should be connected to GND.
Figure 15 - 1024 Channel Switch Matrix
2-111
MITEL [ MITEL NETWORKS CORPORATION ]
