MT9076
Preliminary Information
20.1.5 Per Channel Transmit signaling (Pages 5 and 6) (T1)
Page 05H, addresses 10000 to 11111, and page 06H addresses 10000 to 10111 contain the Transmit signaling
Control Words for DS1 channels 1 to 16 and 17 to 24 respectively. Table 80 illustrates the mapping between the
addresses of these pages and the DS1 channel numbers. Control of these bits for any one channel is through
the processor or controller port when the Per Time Slot Control bit RPSIG bit is high. Table 81 describes bit
allocation within each of these registers.
Page 5 Address:
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15
Equivalent DS1
channel
10 11 12 13 14 15 16
Page 6 Address:
0
1
2
3
4
5
6
7
8
x
9
x
10 11 12 13 14 15
Equivalent DS1
channel
17 18 19 20 21 22 23 24
x
x
x
x
x
x
Table 79 - Page 5, 6 Address Mapping to DS1 Channels (T1)
Bit
Name
Functional Description
7 - 4
3
- - -
Unused.
Transmit signaling Bits A for Channel n. Where signaling is enabled, these bits are
A(n)
transmitted in bit position 8 of the 6th DS1 frame (within the 12 frame superframe structure
for D4 superframes and the 24 frame structure for ESF superframes).
2
1
0
B(n)
C(n)
D(n)
Transmit signaling Bits B for Channel n. Where signaling is enabled, these bits are
transmitted in bit position 8 of the 12th DS1 frame (within the 12 frame superframe structure
for D4 superframes and the 24 frame structure for ESF superframes).
Transmit signaling Bits C for Channel n. Where signaling is enabled, these bits are
transmitted in bit position 8 of the 18th DS1 frame within the 24 frame structure for ESF
superframes. In D4 mode these bits are unused.
Transmit signaling Bits D for Channel n. Where signaling is enabled, these bits are
transmitted in bit position 8 of the 24th DS1 frame within the 24 frame structure for ESF
superframes. In D4 mode these bits are unused.
Table 80 - Transmit Channel Associated signaling (T1) (Pages 5,6)
Serial per channel transmit signaling control through CSTi is selected when the Per Time Slot Control bit
RPSIG bit is low. Table 82 describes the bit allocation within each of the 24 active ST-BUS time slots of CSTi.
88
MITEL [ MITEL NETWORKS CORPORATION ]
