MT9076
Preliminary Information
Bit
Name
Functional Description
7
HDLC0I HDLC0 Interrupt. Whenever an unmasked HDLC0 interrupt occurs this bit goes high.
Reading this register clears this bit.
6
5
4
HDLC1I HDLC1 Interrupt. Whenever an unmasked HDLC1 interrupt occurs this bit goes high.
Reading this register clears this bit.
HDLC2I HDLC2 Interrupt. Whenever an unmasked HDLC2 interrupt occurs this bit goes high.
Reading this register clears this bit.
LCDI
Loop Code Detected Interrupt. When unmasked this interrupt bit goes high whenever
either the loop up (00001) or loop down (001) code has been detected on the line for a
period of 48 milliseconds. Reading this register clears this bit.
3
1SECI
One Second Status Interrupt. When unmasked this interrupt bit goes high whenever
the 1SEC status bit (page 3 address 12H bit 7) goes from low to high. Reading this
register clears this bit.
2
1
5SECI
BIOMI
Five Second Status Interrupt. When unmasked this interrupt bit goes high whenever
the 5 SEC status bit goes from low to high. Reading this register clears this bit.
Bit Oriented Message Interrupt. When unmasked this interrupt bit goes high whenever
a pattern 111111110xxxxxx0 has been received on the FDL that is different from the last
message. The new message must persist for 8 out the last 10 message positions to be
accepted as a valid new message. Reading this register clears this bit.
0
SIGI
signaling Interrupt. When unmasked this interrupt bit goes high whenever a change of
state (optionally debounced - see DBEn in the Data Link, signaling Control Word page 1
address 12H) is detected in the signaling bits (AB or ABCD) pattern. Reading this register
clears this bit.
Table 77 - Interrupt Word Three
(Page 4, Address 1EH) (T1)
86
MITEL [ MITEL NETWORKS CORPORATION ]
