Preliminary Information
MT9076
ST-BUS Bit
Stream
Bit Cell
Bit Cell
Bit Cell
t
FPH
F0b
(Input)
V
V
TT
TT
t
FPL
t
FPS
t
4WI
t
4WI
C4b
(Input)
t
SIH
All Input
Streams
V
V
TT
t
SIS
t
SOD
All Output
Streams
V
TT, CT
Figure 27 - ST-BUS Timing Diagram (Input Clocks)
ST-BUS Bit
Stream
Bit Cell
Bit Cell
Bit Cell
F0b
(Output)
V
TT
t
t
4WO
FPD
t
FPD
C4b
(Output)
V
TT
t
t
4WO
SIH
All Input
Streams
V
TT
t
t
SIS
SOD
All Output
Streams
V
V
TT, CT
Figure 28 - ST-BUS Timing Diagram (Output Clocks)
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