Preliminary Information
Framing Algorithm
T1/J1 Mode
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Synchronizes with D4 or ESF protocols
Supports SLC-96 framing
Framing circuit is off-line
Transparent transmit and receive modes
In D4 mode the Fs bits can optionally be
cross checked with the Ft bits
The start of the ESF multiframe can be
determined by the following methods:
• Free-run
• Software reset
• Synchronized to the incoming multiframe
An automatic reframe is initiated if the
framing bit error density exceeds the
programmed threshold
In transparent mode, no reframing is forced
by the device
Software can force a reframe at any time
In ESF mode the CRC-6 bits can be
optionally confirmed before forcing a new
frame alignment
During a reframe the signaling bits are frozen
and error counting for Ft, Fs, ESF framing
pattern and CRC-6 bits is suspended
If J1 CRC-6 is selected the Fs bits are
included in the CRC-6 calculation
J1 CRC-6 and J1 Yellow Alarm can be
independently selected
Supports robbed bit signaling
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E1 Mode
MT9076
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MT9076 contains 3 distinct and independent
framing algorithms
1. Basic frame alignment
2. Signaling multiframe alignment
3. CRC-4 multiframe alignment
Transparent transmit and receive modes
Automatic interworking between interfaces
with and without CRC-4 processing
capabilities is supported
An automatic reframe is forced if 3
consecutive frame alignment patterns or
three consecutive non-frame alignment bits
are received in error
In transparent mode, no reframing is forced
by the device
Software can force a reframe at any time
Software can force a multiframe reframe at
any time
E-bits can optionally be set to zero until CRC
synchronization is achieved
Optional automatic RAI
Supports CAS multiframing
Optional automatic Y-bit to indicate CAS
multiframe alignment
Line Coding
T1/J1 Mode
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B8ZS or AMI line coding
Pulse density enforcement
Forced ones insertion
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E1 Mode
HDB3 or AMI line coding
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