Preliminary Information
MT9075B
AUTC
0
ARAI
0
TALM
x
Description
Automatic CRC-interworking is activated. If no valid CRC MFAS is
being received, transmit RAI will flicker high with every reframe (8
msec.), this cycle will continue for 400 msec., then transmit RAI will be
low continuously. The device will stop searching for CRC MFAS,
continue to transmit CRC-4 remainders, stop CRC-4 processing
indicate CRC-to-non-CRC operation and transmit E-bits to be the same
state as the TE control bit (page 01H, address 16H).
Automatic CRC-interworking is activated. Transmit RAI is low
continuously upon loss of synchronization.
Automatic CRC-interworking is activated. Transmit RAI is high
continuously upon loss of synchronization.
Automatic CRC-interworking is de-activated. If no valid CRC MFAS is
being received, transmit RAI flickers high with every reframe (8 msec.),
this cycle continues for 400 msec., then transmit RAI becomes high
continuously. The device continues to search for CRC MFAS and
transmit E-bits are the same state as the TE control bit. When
CRCSYN = 0, the CRC MFAS search is terminated and the transmit
RAI goes low.
Automatic CRC-interworking is de-activated. Transmit RAI is low
continuously upon loss of synchronization.
Automatic CRC-interworking is de-activated. Transmit RAI is high
continuously upon loss of synchronization.
0
0
1
1
1
0
0
1
x
1
1
1
1
0
1
Table 4 - Operation of AUTC, ARAI and TALM Control Bits
There are two CRC multiframe alignment algorithm
options selected by the AUTC control bit (address
11H, page 01H). When AUTC is zero and CSYN is
zero, automatic CRC-to-non-CRC interworking is
selected, if CRC-4 multiframe alignment is not found
in 400 msec, the status bit CRCIWK (page 03H,
address 10H) is set low and no further attempt to
achieve CRC-4 synchronization is made as long as
the
device
remains
in
terminal
frame
synchronization. When AUTC is one and CSYN is
zero, a reframe will be initiated every 8 msec if the
MT9075B achieves terminal frame synchronization,
but fails to achieve CRC-4 synchronization. In this
case, if ARAI is low, RAI will flicker high with every
reframe. If CRC MFAI is unsuccessful after 400ms,
RAI will stay high continuously.
The control bit for transmit E bits (TE, bit 4 at
address 16H of page 01H) will have the same
function in both states of AUTC. That is, when CRC-4
synchronization is not achieved the state of the
transmit E-bits will be the same as the state of the TE
control bit. When CRC-4 synchronization is achieved
the transmit E-bits will function as per ITU-T G.704.
Table 4 outlines the operation of the AUTC, ARAI and
TALM control bits of the MT9075B.
CAS Signalling Multiframing
The purpose of the signalling multiframing algorithm
is to provide a scheme that will allow the association
of a specific ABCD signalling nibble with the
appropriate PCM 30 channel. Time slot 16 is
reserved for the communication of Channel
Associated Signalling (CAS) information (i.e., ABCD
signalling bits for up to 30 channels). Refer to ITU-T
G.704 and G.732 for more details on CAS
multiframing requirements.
A CAS signalling multiframe consists of 16 basic
frames (numbered 0 to 15), which results in a
multiframe repetition rate of 2 msec. It should be
noted that the boundaries of the signalling multiframe
may be completely distinct from those of the CRC-4
multiframe. CAS multiframe alignment is based on a
multiframe alignment signal (a 0000 bit sequence),
which occurs in the most significant nibble of time
slot 16 of basic frame 0 of the CAS multiframe. Bit 6
of this time slot is the multiframe alarm bit (usually
designated Y). When CAS multiframing is acquired
on the receive side, the transmit Y-bit is zero; when
CAS multiframing is not acquired, the transmit Y-bit is
13
MITEL [ MITEL NETWORKS CORPORATION ]
