MT9075A
Preliminary Information
†
AC Electrical Characteristics - Intel Microprocessor Timing
‡
Characteristics
Sym Min Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
9
RD low
t
60
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RDL
RD High
CS Setup
CS Hold
t
RDH
t
CSS
t
0
CSH
Address Setup
t
10
15
80
80
10
10
110
ADS
ADH
DDR
Address Hold
t
Data Delay Read
Data Active to High Z Delay
Data Setup Write
t
CL=50pF, R =1kΩ.
L
t
DAZ
DSW
DHW
t
10 Data Hold Write
t
*
11 Cycle Time
t
CYC
† Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage
‡Typical figures are at 25˚C and are for design aid only: not guaranteed and not subject to production testing.
* This cycle time is for all accesses other than HDLC FIFOs. For HDLC FIFO accesses, a minimum 100ns wait state is required between
successive Read/Write operations.
t
CYC
t
RDL
RD
CS
V
V
V
TT
TT
TT
t
RDH
t
t
t
CSS
CSH
CSH
WR
t
t
ADH
t
ADS
ADH
A0-A4
V
V
TT
t
DDR
t
DAZ
VALID DATA
D0-D7
READ
V
TT, CT
t
t
DSW
DHW
D0-D7
WRITE
VALID DATA
V
TT
Figure 12 - Intel Microprocessor Timing
4-196
MITEL [ MITEL NETWORKS CORPORATION ]
