Preliminary Information
MT9075A
Bit
Name
Functional Description
Bit
Name
Functional Description
7
1SEC One Second Timer Status. This bit
changes state once every 0.5
second and is synchronous with the
2SEC timer. This feature is not
available when the device is
operated in freerun mode.
7
RIU1
Receive International Use 1. This
bit is received on the PCM 30 2048
kbit/sec. link in bit position one of
the non-frame alignment signal. It is
used
for
CRC-4
multiframe
alignment or international use.
6
5
2SEC Two Second Timer Status. This bit
changes state once every second
and is synchronous with the 1SEC
timer. This feature is not available
when the device is operated in
freerun mode.
6
RNFAB Receive Non-frame Alignment
Bit. This bit is received on the PCM
30 2048 kbit/sec. link in bit position
two of the non-frame alignment
signal. This bit should be one in
order to differentiate between
frame alignment frames and non-
frame alignment frames.
T1
Timer One. This bit will be high
upon loss of terminal frame
synchronization persisting for 100
msec. This bit shall be low when T2
becomes high. Refer to I.431
Section 5.9.2.2.3. This feature is not
available when the device is
operated in freerun mode.
5
RALM Receive Alarm. This bit is received
on the PCM 30 2048 kbit/sec. link in
bit position three (the A bit) of the
non-frame alignment signal. It is
used as a remote alarm indication
(RAI) from the far end of the PCM
30 link (1 - alarm, 0 - normal).
4
T2
Timer Two. This bit will be high
when the MT9075A acquires
terminal frame synchronization
persisting for 10 msec. This bit shall
4 - 0 RNU4-8 Receive National Use Four to
Eight. These bits are received on
be
low
when
non-normal
the PCM 30 2048 kbit/sec. link in bit
operational frames are received.
I.431 Section 5.9.2.2.3. This feature
is not available when the device is
operated in freerun mode.
positions four to eight (the S bits)
of the non-frame alignment signal.
a
Table 36 - Receive Non-Frame Alignment Signal
(Page 03H, Address 13H)
3
2
1
400T
8T
400 msec. Timer Status. This bit
changes state when the 400 msec.
CRC-4 multiframe alignment timer
expires.
8 msec. Timer Status. This bit
changes state when the 8 msec.
CRC-4 multiframe alignment timer
expires.
CALN CRC-4 Alignment. This bit changes
state every msec. When CRC-4
multiframe alignment has been
achieved state changes of this bit
are synchronous with the receive
CRC-4 synchronization signal.
0
KLVE Keep Alive. This bit is high when
the AIS status bit (page 03H,
address 19H) has been high for at
least 100msec. This bit will be low
when AIS goes low (I.431).
Table 35 - Timer Status Word
(Page 03H, Address 12H)
4-171
MITEL [ MITEL NETWORKS CORPORATION ]
