MT9075B
Preliminary Information
jittered clock is used to clock the data out of the
FIFO.
MT9075B
20MHz
OSC1
The JA meets the jitter transfer characteristics as
proposed
by
G.823
and
the
relevant
recommendations as shown in Figure 8. The JA
FIFO depth can be selected to be from 16 to 128
words deep, in multiples of 16 (2-bit) words. Its read
pointer can be centered by changing the JFC bit
(address 18H of page 02H) to provide maximum jitter
tolerance. If the read pointer should come within 4
bits of either end of the FIFO, the read clock
frequency will be increased or decreased by 0.0625
UI to correct the situation. The maximum time
56pF
39pF
1MΩ
1µH*
100Ω
OSC2
Note: the 1µH inductor is optional
needed to centre is T
= 3904 Depth ns, where
max
Depth is the selected JA FIFO depth. During this
time the JA will not attenuate jitter.
Figure 7 - Crystal Oscillator Circuit
Jitter Attenuator (JA)
To ensure normal operation, the JA FIFO depth
should be set in software to be larger than the
anticipated maximum UI of input jitter.
The MT9075B Jitter Attenuator (JA), which consists
of a Phase Locked Loop (PLL) and data FIFO, can
be used on either the transmit or receive side of the
interface.
Clock Jitter Attenuation Modes
MT9075B has three basic jitter attenuation modes of
operation, selected by the BS/LS and BL/FR control
pins.
On the transmit side the C4b signal clocks the data
into the FIFO, the PLL de-jitters the C4b clock and
the resulting clean C4b signal clocks the data out of
the FIFO.
•
•
•
System Bus Synchronous Mode.
Line Synchronous Mode.
Free-run mode.
When the JA is selected on the receive side, the
extracted clock signal clocks the data into the FIFO.
The same clock feeds the PLL and the resulting de-
dB
0.5
0
-20 dB/decade
-19.5
10
40
Frequency (Hz)
400
10K
Figure 8 - Typical Jitter Attenuation Curve
10
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