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MT9074AP 参数 Datasheet PDF下载

MT9074AP图片预览
型号: MT9074AP
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1单芯片收发器 [T1/E1/J1 Single Chip Transceiver]
分类和应用: 电信集成电路
文件页数/大小: 122 页 / 371 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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Advance Information  
MT9074  
dB  
-0.5  
0
-20 dB/decade  
19.5  
10  
40  
400  
10K  
Frequency (Hz)  
Figure 11- TR 62411 Jitter Attenuation Curve  
Phase Lock Loop (PLL)  
Mode Name  
BS/LS  
S/FR  
Note  
System Bus  
Synchronous  
1
1
PLL locked to C4b.  
The MT9074 contains a PLL, which can be locked to  
either an input 4.096 Mhz clock or the extracted line  
clock.The PLL will attenuate jitter from less than  
2.5 Hz and roll-off at a rate of 20 dB/decade. Its  
intrinsic jitter is less than 0.02 UI. The PLL will meet  
the jitter transfer characteristics as specified by ATT  
Line Synchronous  
Free-Run  
0
x
1
0
PLL locked to E1.5o.  
PLL free - running.  
Table 5 - Selection of clock jitter attenuation  
modes using the M/S and MS/FR pins  
document  
TR  
62411  
and  
the  
relevant  
recommendations as shown in Figure 11.  
the internal PLL before being used to synchronize  
the transmitted data. The clock extracted (with no  
jitter attenuation performed) from the receive data  
can be monitored on pin E1.5o.  
Clock Jitter Attenuation Modes  
MT9074 has three basic jitter attenuation modes of  
operation, selected by the BS/LS and S/FR control  
pins. Referring to the mode names given in Table 5  
the basic operation of the jitter attenuation modes  
are:  
In Line Synchronous mode, the clock extracted from  
the receive data is dejittered using the internal PLL  
and then output on pin C4b. Pin E1.5o provides the  
extracted receive clock before it has been dejittered.  
The transmit data is synchronous to the clean  
receive clock.  
System Bus Synchronous Mode.  
Line Synchronous Mode.  
Free-run mode.  
In Free-Run mode the transmit data is synchronized  
to the internally generated clock. The internal clock  
is output on pin C4b. The clock signal extracted from  
the receive data is not dejittered and is output  
directly on E1.5o.  
In System Bus Synchronous mode pins C4b and F0b  
are always configured as inputs, while in the Line  
Synchronous and Free-Run modes C4b and F0b are  
configured as outputs.  
Depending on the mode selection above, the PLL  
can either attenuate transmit clock jitter or the  
receive clock jitter. Table 5 shows the appropriate  
configuration of each control pin to achieve the  
In System Bus Synchronous mode an external clock  
is applied to C4b. The applied clock is dejittered by  
13