MT9074
Advance Information
interrupt registers are cleared IRQ will return to a
high impedance state. This function can also be
accomplished by toggling the INTA bit (page 1,
address 1AH).
Interrupts on T1 mode
Interrupt Mask Word Zero
Bit 7
Bit 0
TFSYNI MFSYNI TSAI AISI LOSI SEI TxSLPI RxSLPI
All the interrupts of the MT9074 in T1 and E1 mode
are maskable. This is accomplished through interrupt
mask words zero to three, which are located on page
1, addresses 1BH to 1EH and the (optional) HDLC
interrupt mask located at address 16 of page B.
Interrupt Mask Word One
Bit 7
Bit 0
FEI
CRCI YELI COFAI BPVI PRBSI PDVI
- - -
After a MT9074 reset (RESET pin or RST control bit),
all interrupts are masked.
Interrupt Mask Word Two
Bit 7
Bit 0
All interrupts may be suspended, without changing
the interrupt mask words, by making the SPND
control bit of page 1, address 1AH high.
FEO CRCO OOFO COFAO BPVO PRBSO MFOOFO - - -
Interrupt Mask Word Three
All interrupts are cleared by forcing the pin TxAO low.
Bit 7
Bit 0
- - -
- - -
- - -
LCDI 1SECI 5SECI BIOMI SIGI
HDLC Interrupt Masks
Bit 7
Bit 0
Ga
EOPD TEOP EopR TxFl FATxU RxFf RxOv
Interrupts on E1 mode
Interrupt Mask Word Zero
Bit 7
Bit 0
SYNI MFSYI CSYNI AISI LOSI CEFI
YI
SLPI
Interrupt Mask Word One
Bit 7
Bit 0
FERI CRCI
EBI
AIS16I BPVI PRBSI AUXPI RAII
Interrupt Mask Word Two
Bit 7
Bit 0
FEOM CRCO EBOI - - - BPVO PRBSO PRBSMO - - -
Interrupt Mask Word Three
Bit 7
Bit 0
- - -
- - -
- - -
JAI
1SECI 5SECI RCRI SIGI
HDLC Interrupt Masks
Bit 7
Bit 0
Ga
EOPD TEOP EopR TxFl FATxU RxFf RxOv
40
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