Preliminary Information
Pin Description
Pin #
62
63
64
65
66
67
68
69
70
Name
DIN32K
V
DD
V
SS
FBDATA3
STi0
FBDATA2
DIN8K1
FBDATA1
LLED
Description
MT90710
Asynchronous 32 kHz Signal (Input Type 1).
Transmitted to the far-end DOUT32K
output.
Positive Power Supply.
Nominally 5 volts.
Power Supply Ground.
Nominally 0 volts.
Frame Buffer Data Bit 3 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 3.
Serial, 32 Channel, 2.048 Mb/s Link 0 (Input Type 1).
Frame Buffer Data Bit 2 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 2.
Asynchronous 8 kHz Signal 1 (Input Type 1).
Transmitted to the far-end DOUT8K1
output.
Frame Buffer Data Bit 1 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 1.
"Local Sync" LED Driver (Open Collector, Output Type 2).
Drives the "Local Sync"
LED on/off at approximately a 4 Hz rate when the local interface is not in
synchronization.
Frame Buffer Data Bit 0 (Bidirectional; Input Type 1 and Output Type 2).
Data bit 0.
Reset Control (Input Type 1).
Internally Connected.
Positive Power Supply.
Nominally 5 volts.
No Internal Connection.
Power Supply Ground.
Nominally 0 volts.
Frame Buffer RAM Address Bit 0 (Output Type 2).
Frame Buffer RAM Address Bit 1 (Output Type 2).
Frame Buffer RAM Address Bit 2 (Output Type 2).
Frame Buffer RAM Address Bit 3 (Output Type 2).
Frame Buffer RAM Address Bit 4 (Output Type 2).
Frame Buffer RAM Address Bit 5 (Output Type 2).
Frame Buffer RAM Address Bit 6 (Output Type 2).
Serial, 32 Channel, 2.048 Mb/s Link 6B (Output Type 3).
Output active only when
receiver detects the synchronization pattern on RxDATA input stream; high impedance
output during loss of synchronization.
71
72
73
74
75
76
77
78
79
80
81
82
83
84
FBDATA0
RESET
IC
V
DD
NC
V
SS
FBADDR0
FBADDR1
FBADDR2
FBADDR3
FBADDR4
FBADDR5
FBADDR6
STo6B
Notes:
All unused inputs should be connected to logic high or low unless otherwise stated. All outputs should be left open circuit when not used.
All output types are CMOS with CMOS logic levels (see DC Electrical Characteristics for Type drive capability).
Input Type 1 has TTL compatible logic levels, Type 2 has CMOS compatible logic levels and Type 3 has TTL Schmitt trigger compatible
logic levels (see DC Electrical Characteristics).
Overview
The MT90710 multiplexes multiple Serial Telecom
(ST-BUS timing, Figure 7) links onto a single 20 MHz
loop to facilitate point-to-point data transport
requirements. The MT90710 connects easily with
standard Fiber Optic interfaces to form a complete
electric to photonic conversion circuit. Optical
transmission allows large bandwidth inter-shelf or, in
distributed systems, inter-node communication by
eliminating multiple data busses, cable inter-connect
and the attendant driver interfaces. The final result is
a simple physical interface free of the radiated
emissions and background noise susceptibility
problems
encountered
in
copper-wired
environments.
5-7
MITEL [ MITEL NETWORKS CORPORATION ]
