Advance Information
Pin Description (continued)
Pin #
17
18
19
20
21, 22
23
24, 25
26
Name
C16
V
DD
IC0
IC1
IC0
MS
IC0
FSEL2
Description
MT9041
Clock 16.384 MHz (CMOS compatible).
This output is a 16.384 MHz output clock locked
to the reference input signal.
Positive Supply Voltage.
Nominally +5 volts.
Internal Connection 0.
Connect to V
SS.
Internal Connection 1.
Leave open circuit.
Internal Connection 0.
Connect to V
SS.
Mode Select Input (TTL compatible).
This input selects the PLL mode of operation (i.e. ,
NORMAL or FREERUN, see Table 1).
Internal Connection 0.
Connect to V
SS.
Frequency Select - 2 Input (TTL compatible).
This input, in conjunction with FSEL1,
selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz;
see Table 3).
Frequency Select - 1 Input (TTL compatible).
This input, in conjunction with FSEL2,
selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz;
see Table 3).
Reset (TTL compatible).
This input (active LOW) puts the MT9041 in its reset state. To
guarantee proper operation, the device must be reset after power-up. The time constant for
a power-up reset circuit must be a minimum of five times the rise time of the power supply. In
normal operation, the RST pin must be held low for a minimum of 60 nsec to reset the
device.
27
FSEL1
28
RST
3-85
MITEL [ MITEL NETWORKS CORPORATION ]
