MT90220
Table of Contents
6.0 Support Blocks............................................................................................................................................. 33
6.1 Counter Block........................................................................................................................................... 33
6.1.1 UTOPIA Input I/F counters............................................................................................................... 33
6.1.2 Transmit PCM I/F Counters ............................................................................................................. 33
6.1.3 Receive PCM I/F Counters .............................................................................................................. 33
6.1.4 Access to the Counters.................................................................................................................... 33
6.2 Interrupt Block .......................................................................................................................................... 34
6.2.1 IRQ Master Status and IRQ Master Enable Registers..................................................................... 34
6.2.2 IRQ Link Status and IRQ Link Enable Registers.............................................................................. 35
6.2.2.1 Bit 7 and 6 of IRQ Link 0 Status and IRQ Link 0 Enable Registers .......................................... 35
6.2.3 IRQ Link UNI Overflow and IRQ UTOPIA Input UNI Overflow Status Registers ............................. 36
6.2.4 IRQ IMA Group Overflow Status and Enable Registers................................................................... 36
6.2.5 IRQ IMA Overflow Status and RX UTOPIA IMA Group FIFO Overflow Enable Registers .............. 36
6.3 Register and Memory Map....................................................................................................................... 36
6.3.1 Access to the Various Registers ...................................................................................................... 36
6.3.2 Direct Access ................................................................................................................................... 37
6.3.3 Indirect Access................................................................................................................................. 37
6.3.4 Clearing of Status Bits...................................................................................................................... 37
6.3.4.1 Toggle Bit.................................................................................................................................. 37
6.3.5 Test Modes ...................................................................................................................................... 37
7.0 Register Descriptions.................................................................................................................................. 38
7.1 Utopia Register Description...................................................................................................................... 41
7.2 TX Registers Description.......................................................................................................................... 45
7.3 TX ICP Register Description .................................................................................................................... 50
7.4 RX Registers Description ......................................................................................................................... 52
7.5 RX ICP Cell Registers Description........................................................................................................... 57
7.6 External SRAM Register Description ....................................................................................................... 60
7.7 RX Delay Registers Description............................................................................................................... 62
7.8 RX Recombiner Registers Description..................................................................................................... 65
7.9 TX/RX and PLL Control Registers Description......................................................................................... 67
7.10 Counter Registers Description ................................................................................................................ 73
7.11Interrupt Registers Description................................................................................................................. 75
7.12 Miscellaneous Registers Description ...................................................................................................... 78
8.0 Application Notes......................................................................................................................................... 79
8.1 Connecting the MT90220 to Various T1/E1 Framers............................................................................... 79
9.0 AC/DC Characteristics................................................................................................................................. 85
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